Srdjan Djordjevic
Srdjan Djordjevic, Muenchen DE
Patent application number | Description | Published |
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20090037683 | Semiconductor Memory Arrangement - A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive the command and address signals from the first control device and to transmit the command and address signals to the memory units of the plurality of memory units. | 02-05-2009 |
20090141581 | Semiconductor Memory Arrangement and System - A semiconductor memory arrangement includes a control device with a first port and a second port, the first and second port being adapted to receive command and address signals, a first buffer device being coupled to the first port, a second buffer device being coupled to the second port and a plurality of memory units at least including a first group of memory units and a second group of memory units. | 06-04-2009 |
20090307417 | INTEGRATED BUFFER DEVICE - An integrated buffer device. One embodiment provides a receiving unit and a logic unit to control the operation of the buffer device based on a setting signal. | 12-10-2009 |
Srdjan Djordjevic, Munich DE
Patent application number | Description | Published |
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20080259670 | Memory Module - A memory module having a board and a plurality of memory elements on the board which belong to different memory ranks, each memory rank being addressable via a respective selection signal. The memory module additionally includes a memory buffer having a memory rank interface coupled to the memory elements of each memory rank, and a selection signal output for the selection signal of each memory rank, the memory elements being arranged in rows on the board and the memory elements of a memory rank extending only over half of the rows. | 10-23-2008 |
20090019195 | INTEGRATED CIRCUIT, MEMORY MODULE AND SYSTEM - An integrated circuit comprises a first data interface configured to be coupled to a first memory device, a second data interface configured to be coupled to a second memory device, a first control interface configured to be coupled to the first memory device, and a second control interface configured to be coupled to the second memory device. The control interfaces are arranged between the first data interface and the second data interface or the data interfaces are arranged between the first control interface and the second control interface. | 01-15-2009 |
Srdjan Djordjevic, Munchen DE
Patent application number | Description | Published |
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20080250292 | Memory Module with Ranks of Memory Chips - A memory module includes a plurality of memory devices and a stacked error correction code memory device. The plurality of memory devices includes one or more memory chips arranged in a plurality of ranks. The stacked error correction code memory device includes a plurality of error correction code memory chips. The number of error correction code memory chips is at least one more than the number of the one or more memory chips. Each of the error correction code memory chips are arranged together with the memory chips of one of the ranks. | 10-09-2008 |
20080301370 | Memory Module - A memory module includes a module circuit board, an amplifier circuit disposed on the module circuit board for amplifying an input signal, and a memory component to store a data item, wherein the memory component is disposed on the module circuit board. The amplifier circuit includes an input to receive a data signal and an output to provide an amplified data signal. The memory component comprises an input to receive the amplified data signal, wherein the data item is stored in the memory component in dependence on a level of the received amplified data signal. | 12-04-2008 |