Patent application number | Description | Published |
20140181482 | STORE-TO-LOAD FORWARDING - An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located. | 06-26-2014 |
20140380023 | DEPENDENCE-BASED REPLAY SUPPRESSION - A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit. | 12-25-2014 |
20140380024 | DEPENDENT INSTRUCTION SUPPRESSION - A method includes suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load instruction. A processor includes an execution unit to execute instructions and a scheduler. The scheduler is to select for execution in the execution unit a load instruction having at least one dependent instruction and suppress execution of the at least one dependent instruction using stored dependency information responsive to an invalid status of the load instruction. | 12-25-2014 |
20150026437 | METHOD AND APPARATUS FOR DIFFERENTIAL CHECKPOINTING - A processor core stores information that maps a physical register to an architectural register in response to an instruction modifying the architectural register. The processor recovers a checkpointed state of a set of architectural registers prior to modification of the architectural register by the instruction by modifying a reference mapping of physical registers to the set of architectural registers using the stored information. | 01-22-2015 |
20150026685 | DEPENDENT INSTRUCTION SUPPRESSION - A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction. | 01-22-2015 |
20150026686 | DEPENDENT INSTRUCTION SUPPRESSION IN A LOAD-OPERATION INSTRUCTION - A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status. | 01-22-2015 |
Patent application number | Description | Published |
20140136819 | REGISTER FILE MANAGEMENT FOR OPERATIONS USING A SINGLE PHYSICAL REGISTER FOR BOTH SOURCE AND RESULT - A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid. | 05-15-2014 |
20140351562 | TECHNIQUES FOR SCHEDULING OPERATIONS AT AN INSTRUCTION PIPELINE - A dispatch stage of a processor core dispatches designated operations (e.g. load/store operations) to a temporary queue when the resources to execute the designated operations are not available. Once the resources become available to execute an operation at the temporary queue, the operation is transferred to a scheduler queue where it can be picked for execution. By dispatching the designated operations to the temporary queue, other operations behind the designated operations in a program order are made available for dispatch to the scheduler queue, thereby improving instruction throughput at the processor core. | 11-27-2014 |
Patent application number | Description | Published |
20090026437 | Copper compatible chalcogenide phase change memory with adjustable threshold voltage - A phase change memory cell may include two or more stacked or unstacked series connected memory elements. The cell has a higher, adjustable threshold voltage. A copper diffusion plug may be provided within a pore over a copper line. By positioning the plug below the subsequent chalcogenide layer, the plug may be effective to block copper diffusion upwardly into the pore and into the chalcogenide material. Such diffusion may adversely affect the electrical characteristics of the chalcogenide layer. | 01-29-2009 |
20090196091 | Self-aligned phase change memory - A self-aligned phase change memory may be formed by blanket depositing a number of layers and then using patterning techniques to define the individual cells. In one embodiment, a layer of phase change material may be blanket deposited over a lower electrode material. The structure may then be patterned and etched to form a plurality of spaced, parallel elongate first strips. Those strips may then be covered with a filler material, planarized, and then patterned again in a transverse direction to form a plurality of transverse, spaced, parallel second strips. The resulting structure then has singulated phase change material with connections in at least one of the row or column direction. The singulated the phase change material is self-aligned to underlying and overlying electrodes. | 08-06-2009 |
20090244962 | Immunity of phase change material to disturb in the amorphous phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. | 10-01-2009 |
20090302298 | Forming sublithographic phase change memory heaters - A phase change memory may be formed with a sublithographic heater by using a mask with a sidewall spacer to etch an opening in a dielectric layer. The opening then has a sublithographic lateral extent. The resulting via may be filled with a heater material to form a sublithographic heater. | 12-10-2009 |
20110128770 | STORED MULTI-BIT DATA CHARACTERIZED BY MULTIPLE-DIMENSIONAL MEMORY STATES - Subject matter disclosed herein relates to enhancing data storage density of a memory device. | 06-02-2011 |
20110134685 | Energy-efficient set write of phase change memory with switch - Embodiments of apparatus and methods for an energy efficient set write of phase change memory with switch are generally described herein. Other embodiments may be described and claimed. | 06-09-2011 |
20110147695 | FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS - In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed. | 06-23-2011 |
20110240943 | Immunity of Phase Change Material to Disturb in the Amorphous Phase - Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb. | 10-06-2011 |
20120225534 | SELF-ALIGNED CROSS-POINT PHASE CHANGE MEMORY-SWITCH ARRAY - Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same. | 09-06-2012 |
20120282752 | FABRICATING CURRENT-CONFINING STRUCTURES IN PHASE CHANGE MEMORY SWITCH CELLS - In one or more embodiments, methods of fabricating current-confining stack structures in a phase change memory switch (PCMS) cell are provided. One embodiment shows a method of fabricating a PCMS cell with current in an upper chalcogenide confined in the row and column directions. In one embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension memory chalcogenide are shown. In another embodiment, methods of fabricating a PCMS cell with sub-lithographic critical dimension middle electrode heaters are disclosed. | 11-08-2012 |
20120294076 | Forming Sublithographic Heaters for Phase Change Memories - A phase change memory with a heater with sublithographic dimensions may be achieved, in some embodiments, with lower thermal budget. The phase change memory may use a controlled etching process to reduce the lateral dimension of the heater. | 11-22-2012 |
20120331204 | DRIFT MANAGEMENT IN A PHASE CHANGE MEMORY AND SWITCH (PCMS) MEMORY DEVICE - The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed. | 12-27-2012 |
Patent application number | Description | Published |
20120155161 | THREE-TERMINAL OVONIC THRESHOLD SWITCH AS A CURRENT DRIVER IN A PHASE CHANGE MEMORY - A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the third terminal of the three-terminal OTS. A method of making the three-terminal OTS is also presented. | 06-21-2012 |
20120243306 | METHOD AND APPARATUS TO RESET A PHASE CHANGE MEMORY AND SWITCH (PCMS) MEMORY CELL - The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, the non-volatile memory of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a process for resetting the PCMS memory utilizing a “look-up” table to calculate a current required to place a bit above a reference level to maximum threshold voltage. | 09-27-2012 |
20130283936 | MATERIAL TEST STRUCTURE - Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material. | 10-31-2013 |
20130294152 | APPARATUSES AND METHODS INCLUDING MEMORY ACCESS IN CROSS POINT MEMORY - Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described. | 11-07-2013 |