Patent application number | Description | Published |
20100093130 | Methods of forming multi-level cell of semiconductor memory - Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided. | 04-15-2010 |
20100190321 | METHOD OF FABRICATING PHASE-CHANGE MEMORY DEVICE HAVING TiC LAYER - Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode. | 07-29-2010 |
20100220520 | Multi-bit phase change memory devices - A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material. | 09-02-2010 |
20110049458 | Non-volatile memory device including phase-change material - A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by Sn | 03-03-2011 |
20110049459 | NON-VOLATILE MEMORY DEVICE INCLUDING PHASE-CHANGE MATERIAL - A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I) | 03-03-2011 |
20110284815 | PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS - A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region. | 11-24-2011 |
20120313066 | NONVOLATILE MEMORY DEVICES, NONVOLATILE MEMORY CELLS AND METHODS OF MANUFACTURING NONVOLATILE MEMORY DEVICES - A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film. | 12-13-2012 |
20130017663 | METHOD OF FORMING A PHASE CHANGE MATERIAL LAYER PATTERN AND METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICEAANM PARK; JEONG-HEEAACI HWASEONG-SIAACO KRAAGP PARK; JEONG-HEE HWASEONG-SI KRAANM PARK; SOON-OHAACI SUWON-SIAACO KRAAGP PARK; SOON-OH SUWON-SI KRAANM PARK; JUNG-HWANAACI SEOULAACO KRAAGP PARK; JUNG-HWAN SEOUL KRAANM OH; JIN-HOAACI SEONGNAM-SOAACO KRAAGP OH; JIN-HO SEONGNAM-SO KR - A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening. | 01-17-2013 |
20130171743 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic device and a method of manufacturing the same. In the method, a lower magnetic layer, an insulation layer, and an upper magnetic layer are sequentially formed on a substrate. An upper magnetic layer pattern is formed by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed. An isolation layer pattern is formed from portions of the insulation layer and the lower magnetic layer by performing an oxidation process on the exposed upper surface of the insulation layer, and an insulation layer pattern and a lower magnetic layer pattern are formed from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed. | 07-04-2013 |