Patent application number | Description | Published |
20110163449 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 07-07-2011 |
20110272765 | MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION - A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals. | 11-10-2011 |
20120205727 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER - A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device. | 08-16-2012 |
20120326217 | SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER - A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device. | 12-27-2012 |
20130140681 | SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES - In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region. | 06-06-2013 |
20140027865 | MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION - A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals. | 01-30-2014 |
20140070414 | Semiconductor plural gate lengths - Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask. | 03-13-2014 |
20140117421 | SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE - A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. | 05-01-2014 |
20140162447 | FINFET HYBRID FULL METAL GATE WITH BORDERLESS CONTACTS - A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities. | 06-12-2014 |
20140329388 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer. | 11-06-2014 |
20140377927 | SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE - A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material. | 12-25-2014 |