Patent application number | Description | Published |
20080202258 | MEMS SHOCK SENSORS - A shock sensor comprises a substrate and at least one flexure coupled to the substrate and configured to deflect upon an application of force to the shock sensor sufficient to deflect the flexure. Deflection of the at least one flexure produces a detectable change in an electrical property of the shock sensor. Examples of detectable changes in an electrical property of the shock sensor include an open circuit condition, a closed circuit condition, and a variation in voltage of a piezo-electric detector. In some embodiments, the change in the electrical property of the shock sensor may be remotely read by interrogation of a radio frequency identification transponder positioned on the substrate using a remote radio frequency identification transceiver. The disclosure also relates to a shock sensing system and method of shock detection. | 08-28-2008 |
20080225426 | Magnetic recording device including a thermal proximity sensor - A system includes a magnetic device for writing to and reading from a magnetic medium and a sensor disposed adjacent to the magnetic device and proximate to the magnetic medium. The sensor generates signals related to thermal variations in the sensor caused by changes in a distance between the magnetic device and the magnetic medium. | 09-18-2008 |
20080225584 | Magnetic storage element responsive to spin polarized current - The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the first reference layer and second reference layer and has a third magnetization direction about 45° from the first magnetization direction and about 135° from the second magnetization direction when the memory cell is in a first data state, and a fourth magnetization direction opposite the third magnetization direction when the memory cell is in a second data state. | 09-18-2008 |
20090174968 | MAGNETIC SENSING DEVICE WITH REDUCED SHIELD-TO-SHIELD SPACING - A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing. | 07-09-2009 |
20090184930 | POSITION DETECTING DISPLAY PANEL - An array of sensors, which is coupled to an array of pixel elements in a position detecting display panel, includes sensors that are each registered with a corresponding pixel element of the array of pixel elements, and that each include a material exhibiting magneto-electric behavior in response to a magnetic field source. Some systems may include the position detecting display panel and at least one separate stylus, which includes the magnetic field source. A voltage source, that is operably coupled to each sensor and each pixel element, applies a voltage across one or more particular pixel elements, according to the magneto-electric behavior of the corresponding sensor(s), when the magnetic field source is brought into proximity the corresponding sensor(s). | 07-23-2009 |
20090185315 | MAGNETIC SENSOR INCLUDING A FREE LAYER HAVING PERPENDICULAR TO THE PLANE ANISOTROPY - A magnetic sensor includes a reference layer having a first magnetization direction and a free layer assembly having an effective magnetization direction substantially perpendicular to the first magnetization direction and substantially perpendicular to a plane of each layer of the free layer assembly. A spacer layer is between the reference layer and the free layer, and a signal enhancement layer is exchange coupled to the free layer assembly on a side opposite the spacer layer. | 07-23-2009 |
20090242764 | SPIN-TORQUE PROBE MICROSCOPE - A spin-torque probe microscope and methods of using the same are described. The spin-torque probe microscope includes a cantilever probe body, a magnetic tip disposed at a distal end of the cantilever probe body, an electrically conductive sample disposed proximate to the magnetic tip, an electrical circuit providing a spin-polarized electron current to the electrically conductive sample, and a vibration detection element configured to sense vibration frequency of the cantilever probe body. The spin-polarized electron current is sufficient to alter a local electron spin or magnetic moment within the electrically conductive sample and be sensed by the magnetic tip. | 10-01-2009 |
20090262467 | MAGENTIC JUNCTION MEMORY ARRAY - A magnetic junction memory array and methods of using the same are described. The magnetic junction memory array includes a plurality of electrically conductive word lines extending in a first direction, a plurality of electrically conductive bit lines extending in a second direction and forming a cross-point array with the plurality of electrically conductive word lines, and a memory cell proximate to, at least selected, cross-points forming a magnetic junction memory array. Each memory cell includes a magnetic pinned layer electrically between a magnetic bit and an isolation transistor. The isolation transistor has a current source and a gate. The current source is electrically coupled to the cross-point bit line and the gate is electrically coupled to the cross-point word line. An electrically conductive cover layer is disposed on and in electrical communication with the magnetic bits. | 10-22-2009 |
20090262638 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 10-22-2009 |
20090268352 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 10-29-2009 |
20090283816 | BAND ENGINEERED HIGH-K TUNNEL OXIDES FOR NON-VOLATILE MEMORY - A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials. | 11-19-2009 |
20090289243 | SHORT BRIDGE PHASE CHANGE MEMORY CELLS AND METHOD OF MAKING - Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge. | 11-26-2009 |
20090289290 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-26-2009 |
20090290268 | NONVOLATILE PROGRAMMABLE LOGIC GATES AND ADDERS - Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer. | 11-26-2009 |
20090290411 | WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY - Write verify methods for resistance random access memory (RRAM) are disclosed. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and setting a counter to zero. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value and adding one to the counter. This step is repeated until either the counter reaches a predetermined number or until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value and adding one to the counter. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until either the counter reaches a predetermined number or until all the high resistance state resistance value is less than the upper resistance limit value. | 11-26-2009 |
20090302953 | MAGNETIC OSCILLATOR WITH MULTIPLE COHERENT PHASE OUTPUT - Apparatus to generate signals with multiple phases are described. The apparatus includes a fixed multilayer stack providing a varying magnetic field and at least two sensors adjacent the fixed multilayer stack to sense the varying magnetic field and generate at least two output signals. The frequency of the output signals can be tuned by an input current. | 12-10-2009 |
20090303076 | WIRELESS AND BATTERY-LESS MONITORING UNIT - A wireless and battery-less sensor device is described. The sensor device includes a mechanical energy harvesting device, a sensor electrically coupled to the mechanical energy harvesting module. The sensor is configured to sense with the power supplied by the mechanical energy harvesting device. Nonvolatile memory is configured to store output from the sensor. A radio frequency energy harvesting module is electrically coupled to a radio frequency transmitter. The radio frequency transmitter is configured to transmit the output from the sensor with the power supplied by the radio frequency energy harvesting device. Systems and methods utilizing the wireless and battery-less sensor device are also described. | 12-10-2009 |
20090315088 | FERROELECTRIC MEMORY USING MULTIFERROICS - Ferroelectric memory using multiferroics is described. The multiferrroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A data storage cell having a composite multiferroic layer is adjacent to the electrically insulating layer. The electrically insulating layer separated the data storage cell form the channel region. A control gate electrode is adjacent to the data storage cell. The data storage cell separates at least a portion of the control gate electrode from the electrically insulating layer. | 12-24-2009 |
20090316462 | MAGNETIC TRACKS WITH DOMAIN WALL STORAGE ANCHORS - Magnetic shift registers in which data writing and reading is accomplished by moving the magnetic domain walls by electric current. Various embodiments of domain wall nodes or anchors that stabilize a domain wall are provided. In some embodiments, the wall anchors are elements separate from the magnetic track. In other embodiments, the wall anchors are disturbances in the physical configuration of the magnetic track. In still other embodiments, the wall anchors are disturbances in the material of the magnetic track. | 12-24-2009 |
20090316937 | MONOLITHIC MICRO MAGNETIC DEVICE - A micro magnetic device having a body defining at least part of an enclosed chamber, a pole comprising a soft magnetic material within the chamber, and an electrically conductive coil positioned around the pole. A diaphragm integral with the body defines a top of the chamber opposite the pole. The diaphragm supports a permanent magnetic film. Multiple micro magnetic devices can be combined to form an array. The micro magnetic device may be, for example, a speaker or a sensor. The micro magnetic device may be made by MEMS or thin film techniques. | 12-24-2009 |
20100006813 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed. | 01-14-2010 |
20100032636 | NON-VOLATILE MEMORY CELL WITH ENHANCED FILAMENT FORMATION CHARACTERISTICS - Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode. | 02-11-2010 |
20100033872 | PATTERNED MEDIA BITS WITH CLADDING SHELL - A bit patterned media (BPM) includes many magnetic dots arranged in tracks on a substrate. The magnetic dots each have a hard magnetic core, a soft magnetic cladding surrounding the core and a thin non-magnetic layer that separates the hard magnetic core from the soft magnetic ring. The soft magnetic cladding stabilizes the magnetization at the edges of the hard magnetic core to improve the signal to noise ratio of the magnetic dots. The soft magnetic rings also narrow the magnetic field of the dots which reduces the space requirements and allows more dots to be placed on the substrate. | 02-11-2010 |
20100034010 | MEMORY DEVICES WITH CONCENTRATED ELECTRICAL FIELDS - Designs of resistance memory and phase change memory devices with memory cells having metallic inclusion at least in the area of electrode/medium layer interfaces. Such metallic inclusion is used to concentrate electric fields during writing. Consequently, resistance switching for the devices primarily occurs in the area of the metallic inclusion. As a result, better control of the resistance switching can be attained, thereby optimizing performance of the memory devices. | 02-11-2010 |
20100037102 | FAULT-TOLERANT NON-VOLATILE BUDDY MEMORY STRUCTURE - Various embodiments of the present invention are generally directed to an apparatus and method for providing a fault-tolerant non-volatile buddy memory structure, such as a buddy cache structure for a controller in a data storage device. A semiconductor memory array of blocks of non-volatile resistive sense memory (RSM) cells is arranged to form a buddy memory structure comprising a first set of blocks in a first location of the array and a second set of blocks in a second location of the array configured to redundantly mirror the first set of blocks. A read circuit decodes a fault map which identifies a defect in a selected one of the first and second sets of blocks and concurrently outputs data stored in the remaining one of the first and second sets of blocks responsive to a data read operation upon said buddy memory structure. | 02-11-2010 |
20100038735 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 02-18-2010 |
20100053822 | STRAM CELLS WITH AMPERE FIELD ASSISTED SWITCHING - A magnetic tunnel junction cell that has a ferromagnetic pinned layer, a ferromagnetic free layer, and a non-magnetic barrier layer therebetween. The free layer has a larger area than the pinned layer, in some embodiments at least twice the size of the pinned layer, in some embodiments at least three times the size of the pinned layer, and in yet other embodiments at least four times the size of the pinned layer. The pinned layer is offset from the center of the free layer. The free layer has a changeable vortex magnetization, changeable between clockwise and counterclockwise directions. | 03-04-2010 |
20100054026 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line and a magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line. A write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell. The magnetic tunnel junction data cell is read by a read current passing though the magnetic tunnel junction data cell. | 03-04-2010 |
20100057984 | MEMORY HIERARCHY CONTAINING ONLY NON-VOLATILE CACHE - A storage system that includes non-volatile main memory; non-volatile read cache; non-volatile write cache; and a data path operably coupled between the non-volatile write cache and the non-volatile read cache, wherein the storage system does not include any volatile cache and methods for retrieving and writing data throughout this memory hierarchy system. | 03-04-2010 |
20100058125 | DATA DEVICES INCLUDING MULTIPLE ERROR CORRECTION CODES AND METHODS OF UTILIZING - A method of utilizing at least one block of data, wherein the at least one block of data includes a plurality of cells for storing data and at least one error flag bit, the method including: scanning the block of data for errors; determining the error rate of the block of data; and applying an error correction code to data being read from or written to a cell within the at least one block of data, wherein the error correction code is applied based on the error rate, wherein a weak error correction code is applied when the error rate is below an error threshold, and a strong error correction code is applied when the error rate is at or above the error threshold. | 03-04-2010 |
20100067288 | MEMORY DEVICE STRUCTURES INCLUDING PHASE-CHANGE STORAGE CELLS - A conductive write line of a memory device includes a resistive heating portion for setting and resetting a phase-change material (PCM) storage cell of the device. A dielectric interface extends between the resistive heating portion of the write line and a side of the storage cell, and provides electrical insulation while allowing for thermal coupling between the resistive heating portion and the storage cell. A width of the resistive heating portion of the write line may be less than a width of the storage cell and/or may be less than a width of adjacent portions of the write line, between which the resistive heating portion extends. The side of the storage cell may define a channel of the storage cell through which the write line passes, such that the resistive heating portion is located within the channel. | 03-18-2010 |
20100090300 | MRAM CELLS INCLUDING COUPLED FREE FERROMAGNETIC LAYERS FOR STABILIZATION - A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling. | 04-15-2010 |
20100097852 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. | 04-22-2010 |
20100117169 | MEMORY CELL WITH RADIAL BARRIER - Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization. | 05-13-2010 |
20100135072 | Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current - Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation. | 06-03-2010 |
20100182837 | MAGNETIC FLOATING GATE MEMORY - An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element. | 07-22-2010 |
20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 08-05-2010 |
20100208513 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 08-19-2010 |
20100246245 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 09-30-2010 |
20110026302 | WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY - Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. This step is repeated until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until all the high resistance state resistance value is less than the upper resistance limit value. | 02-03-2011 |
20110058409 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. | 03-10-2011 |
20110069537 | Magnetic Storage Element Responsive to Spin Polarized Current - The present invention relates to a memory cell including a first reference layer having a first magnetization with a first magnetization direction and a second reference layer having a second magnetization with a second magnetization direction substantially perpendicular to the first magnetization direction. A storage layer is disposed between the first reference layer and second reference layer and has a third magnetization direction about 45° from the first magnetization direction and about 135° from the second magnetization direction when the memory cell is in a first data state, and a fourth magnetization direction opposite the third magnetization direction when the memory cell is in a second data state. | 03-24-2011 |
20110075472 | MAGNETORESISTIVE DEVICE HAVING SPECULAR SIDEWALL LAYERS - A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall. | 03-31-2011 |
20110090733 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 04-21-2011 |
20110121418 | MRAM Cells Including Coupled Free Ferromagnetic Layers for Stabilization - A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling. | 05-26-2011 |
20110164335 | MAGNETIC SENSOR INCLUDING A FREE LAYER HAVING PERPENDICULAR TO THE PLANE ANISOTROPY - A magnetic sensor includes a reference layer having a first magnetization direction and a free layer assembly having an effective magnetization direction substantially perpendicular to the first magnetization direction and substantially perpendicular to a plane of each layer of the free layer assembly. A spacer layer is between the reference layer and the free layer, and a signal enhancement layer is exchange coupled to the free layer assembly on a side opposite the spacer layer. | 07-07-2011 |
20110193148 | MAGNET-ASSISTED TRANSISTOR DEVICES - A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device. | 08-11-2011 |
20110199832 | MAGNETIC FLOATING GATE MEMORY - An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element. | 08-18-2011 |
20110205788 | Spin-Torque Bit Cell With Unpinned Reference Layer and Unidirectional Write Current - Method and apparatus for using a uni-directional write current to store different logic states in a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, the memory cell has an unpinned ferromagnetic reference layer adjacent a cladded conductor, a ferromagnetic storage layer and a tunneling barrier between the reference layer and the storage layer. Passage of a current along the cladded conductor induces a selected magnetic orientation in the reference layer, which is transferred through the tunneling barrier for storage by the storage layer. Further, the orientation of the applying step is provided by a cladding layer adjacent a conductor along which a current is passed and the current induces a magnetic field in the cladding layer of the selected magnetic orientation. | 08-25-2011 |
20110254113 | ST-RAM MAGNETIC ELEMENT CONFIGURATIONS TO REDUCE SWITCHING CURRENT - In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer. | 10-20-2011 |
20110267873 | NON-VOLATILE MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A second insulating layer is over the substrate and between the source region and drain region. A solid electrolyte layer is between the first insulating layer and second insulating layer. The solid electrolyte layer has a capacitance that is controllable between at least two states. A first electrode is electrically coupled to a first side of the solid electrolyte layer and is electrically coupled to a voltage source. A second electrode is electrically coupled to a second side of the solid electrolyte layer and is electrically coupled to the voltage source. Multi-bit memory units are also disclosed. | 11-03-2011 |
20120061783 | MEMORY CELL WITH RADIAL BARRIER - Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization. | 03-15-2012 |
20120069630 | WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY - Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. | 03-22-2012 |
20120104348 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 05-03-2012 |
20120127786 | FLUX PROGRAMMED MULTI-BIT MAGNETIC MEMORY - An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed. | 05-24-2012 |
20120134200 | Magnetic Memory Cell With Multi-Level Cell (MLC) Data Storage Capability - Method and apparatus for writing data to a magnetic memory element, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a multi-level cell (MLC) magnetic memory cell stack has first and second magnetic memory elements connected to a first control line and a switching device connected to a second control line. The first memory element is connected in parallel with the second memory element, and the first and second memory elements are connected in series with the switching device. The first and second memory elements are further disposed at different non-overlapping elevations within the stack. Programming currents are passed between the first and second control lines to concurrently set the first and second magnetic memory elements to different programmed resistances. | 05-31-2012 |
20120261778 | SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME - Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. | 10-18-2012 |
20130003448 | MRAM DIODE ARRAY AND ACCESS METHOD - A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. | 01-03-2013 |
20130187115 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters. | 07-25-2013 |
20130188419 | MEMORY WITH SEPARATE READ AND WRITE PATHS - A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. | 07-25-2013 |