Patent application number | Description | Published |
20100327422 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME, AND STACK MODULE AND MEMORY CARD INCLUDING THE SAME - A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided. | 12-30-2010 |
20110097846 | SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug. | 04-28-2011 |
20110284936 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer. | 11-24-2011 |
20130221519 | SEMICONDUCTOR DEVICES INCLUDING DUMMY SOLDER BUMPS - A semiconductor device includes a substrate on which integrated circuit units are formed, main solder bumps that are electrically connected to the integrated circuit units on the substrate and dummy solder bumps that are not electrically connected to the integrated circuit units on the substrate. The dummy solder bumps are narrower than wiring patterns immediately below the dummy solder bumps. | 08-29-2013 |
20130264720 | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages - A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. | 10-10-2013 |
20130313722 | THROUGH-SILICON VIA (TSV) SEMICONDUCTOR DEVICES HAVING VIA PAD INLAYS - A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer. | 11-28-2013 |
20140124901 | INTEGRATED CIRCUIT CHIPS HAVING VERTICALLY EXTENDED THROUGH-SUBSTRATE VIAS THEREIN - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 05-08-2014 |
20140329382 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BUMP - Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess. | 11-06-2014 |
Patent application number | Description | Published |
20080251939 | CHIP STACK PACKAGE AND METHOD OF FABRICATING THE SAME - A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region. | 10-16-2008 |
20090008790 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole. | 01-08-2009 |
20090085224 | STACK-TYPE SEMICONDUCTOR PACKAGE - Provided is a stack-type semiconductor package including a base chip having a circuit formed on one of its surfaces, at least one stack chip having a circuit stacked on the base chip, an adhesive interposed between the base chip and the stack chip, and signal transmission members formed along a lateral surface of the stack chip. The fabrication process of this stack-type semiconductor package may be simplified and the number of process operations may be lessened, thereby reducing the production time and cost. Also, a state of electrical contact of a terminal with a signal transmission member may be solidified, thereby improving the reliability of the stack-type semiconductor package. Furthermore, new post-type signal transmission members are adopted instead of wires or electrodes so that the structural stability and productivity of the stack-type semiconductor package may be markedly enhanced. | 04-02-2009 |
20090267211 | WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME - Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages. | 10-29-2009 |
20090305502 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 12-10-2009 |
20100096753 | THROUGH-SILICON VIA STRUCTURES PROVIDING REDUCED SOLDER SPREADING AND METHODS OF FABRICATING THE SAME - A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed. | 04-22-2010 |
20110086486 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 04-14-2011 |