Patent application number | Description | Published |
20140018005 | DEVICE, SYSTEM AND METHOD OF WIRELESS COMMUNICATION VIA MULTIPLE ANTENNA ASSEMBLIES - Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of second transmissions from another device via one or more of the quasi-omnidirectional antenna assemblies, and, based on the second transmissions, to select at least one selected transmit antenna assembly for transmitting to the other device and a selected receive antenna assembly for receiving transmissions from the other device. Other embodiments are described and claimed. | 01-16-2014 |
20150111502 | DEVICE, SYSTEM AND METHOD OF WIRELESS COMMUNICATION VIA ONE OR MORE ANTENNA ASSEMBLIES - Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may include a wireless communication unit to transmit and receive signals via one or more quasi-omnidirectional antenna assemblies, wherein the wireless communication unit is to transmit, via each quasi-omnidirectional antenna assembly, a plurality of first transmissions, to receive, in response to the first transmissions, a plurality of second transmissions from another device via one or more of the quasi-omnidirectional antenna assemblies, and, based on the second transmissions, to select at least one selected transmit antenna assembly for transmitting to the other device and a selected receive antenna assembly for receiving transmissions from the other device. Other embodiments are described and claimed. | 04-23-2015 |
Patent application number | Description | Published |
20150242633 | DETECTION AND PREVENTION OF SENSITIVE INFORMATION LEAKS - Examples of techniques for detecting and preventing sensitive information leaks are described herein. In one example, a method for detection of sensitive information leaks comprises computing, via a processor, a set of rules that identify sensitive information, and sending, via the processor, the set of rules to a dispatcher application using a protocol. The method can also include detecting, via the processor, that at least one data block of the transmitted data matches the set of rules, and executing, via the processor, a corrective action in response to detecting that at least one of the transmitted data blocks matches the set of rules. | 08-27-2015 |
20150242639 | DETECTION AND PREVENTION OF SENSITIVE INFORMATION LEAKS - Examples of techniques for detecting and preventing sensitive information leaks are described herein. In one example, a method for detection of sensitive information leaks includes computing, via a processor, a set of rules that identify sensitive information, and sending, via the processor, the set of rules to a dispatcher application using a protocol. The method can also include detecting, via the processor, that at least one data block of the transmitted data matches the set of rules, and executing, via the processor, a corrective action in response to detecting that at least one of the transmitted data blocks matches the set of rules. | 08-27-2015 |
Patent application number | Description | Published |
20080224684 | Device and Method for Compensating for Voltage Drops - A device that includes a voltage supply unit and an integrated circuit, the device is characterized by including a voltage sampling circuit adapted to sample voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and wherein the voltage supply unit is adapted to adjust a supply voltage provided to the integrated circuit in response to at least one sampled voltage. A method for voltage drop compensation; the method includes providing a supply voltage to an integrated circuit; the method is characterized by sampling voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops; and adjusting a supply voltage provided to the integrated circuit in response to at least one sampled voltage. | 09-18-2008 |
20080265674 | System And Method For Controlling Voltage And Frequency In A Multiple Voltage Environment - A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. | 10-30-2008 |
20090134883 | DEVICE AND METHOD FOR TESTING A NOISE IMMUNITY CHARACTERISTIC OF ANALOG CIRCUITS - A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit. The method is characterized by providing, during a test period, a noisy signal to a second input of the internal power supply module; providing a noisy supply voltage to the analog circuit, by the internal power supply module, in response to the noisy signal; and evaluating a noise immunity characteristic of the analog circuit in response to the received signals. | 05-28-2009 |
20100001755 | METHOD FOR TESTING NOISE IMMUNITY OF AN INTEGRATED CIRCUIT AND A DEVICE HAVING NOISE IMMUNITY TESTING CAPABILITIES - A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit. | 01-07-2010 |
20100225346 | DEVICE AND METHOD FOR EVALUATING ELECTROSTATIC DISCHARGE PROTECTION CAPABILITIES - A device and a method for evaluating ESD protection capabilities of an integrated circuit, the method includes: connecting multiple test probe to multiple integrated circuit testing points. The method is characterized by repeating the stages of: (i) charging a discharge capacitor to an ESD protection circuit triggering voltage level; (ii) connecting the discharge capacitor to the integrated circuit during a testing period such as to cause the discharge capacitor to interact with the integrated circuit; (iii) measuring at least one signal of the integrated circuit, during at least a portion of the testing period; and (iv) determining at least one ESD protection characteristic of the integrated circuit in response to the at least one signal. | 09-09-2010 |
20110121818 | INTEGRATED CIRCUIT DIE, AN INTEGRATED CIRCUIT PACKAGE AND A METHOD FOR CONNECTING AN INTEGRATED CIRCUIT DIE TO AN EXTERNAL DEVICE - An integrated circuit die comprises an electronic circuit and one or more output ports for outputting signals from the die via an external impedance, to a load, external from the die. The output port is connected to the electronic circuit. The die is further provided with an on-die sampling oscilloscope circuit connected to the output port, for measuring a waveform of the outputted signals. | 05-26-2011 |
20110156752 | METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL - A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal. | 06-30-2011 |
20120032720 | METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginning of the power gating period. | 02-09-2012 |
20120038367 | CONNECTION QUALITY VERIFICATION FOR INTEGRATED CIRCUIT TEST - An integrated circuit device comprising a semiconductor die contained in a package. The integrated circuit device includes one or more internal connection verification modules for asserting a poor connection signal for the test apparatus in response to a voltage difference between a voltage at a corresponding internal power supply node and a reference voltage, the voltage difference being indicative of a poor connection of power supply to one of power supply terminals on the package. The test apparatus can include an indicator or a sorting element for rejecting or accepting the integrated circuit device in response to logic signals indicative of the presence or absence of a defect accompanied by non-assertion of the poor connection signal, and for processing the integrated circuit device distinctively in response to assertion of the poor connection signal. | 02-16-2012 |
20120169391 | DUTY CYCLE CORRECTOR AND DUTY CYCLE CORRECTION METHOD - The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle. | 07-05-2012 |
20120169411 | DEVICE AND METHOD FOR COMPENSATING FOR VOLTAGE DROPS - A device that includes at least one current consuming component. The device is characterized by including a compensation circuit adapted to compare between a voltage level at a sensing point within an integrated circuit and between a reference voltage derived from a voltage peak level at the sensing point; and to selectively increase the voltage at the sensing point in response to the comparison. A method for compensating for voltage drops in an integrated circuit, the method includes providing at least a first supply voltage to an integrated circuit; the method is characterized by including: comparing between a voltage level at a sensing point within an integrated circuit to a reference voltage derived from a voltage peak level at the sensing point; and selectively increasing the voltage at the sensing point in response to the comparison. | 07-05-2012 |
20130027082 | VOLTAGE LEVEL SHIFTER, DECOUPLER FOR A VOLTAGE LEVEL SHIFTER, AND VOLTAGE SHIFTING METHOD - A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node. A second switch is connected to the feedback voltage loop and arranged to couple the input port to the node based on a voltage at the input port and the feedback voltage. A decoupler and a voltage shifting method are also disclosed. | 01-31-2013 |
20130027109 | VOLTAGE LEVEL SHIFTER HAVING A FIRST OPERATING MODE AND A SECOND OPERATING MODE - Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode. | 01-31-2013 |
Patent application number | Description | Published |
20100019836 | INTEGRATED CIRCUIT AND A METHOD FOR RECOVERING FROM A LOW-POWER PERIOD - An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period. The first portion of the power grid is characterized by intrinsic capacitance that is larger that the intrinsic capacitance of the second portion of the power grid. | 01-28-2010 |
20100109633 | INTEGRATED CIRCUIT AND A METHOD FOR RECOVERING FROM A LOW-POWER PERIOD - A system that has low power recovery capabilities, the system includes: a switch that is adapted to provide a gated power supply to a power gated circuit in response to a control current; and a control signal generator adapted to control an intensity of the control current in response to a reception of a low power period end indicator, a value of the continuous supply voltage at a port of the control signal generator, a value of the gated supply voltage and an output signal of a high switching point buffer that is inputted by the gated supply voltage. | 05-06-2010 |
20110291740 | METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT - An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator. | 12-01-2011 |
20140077598 | VOLTAGE REGULATING CIRCUIT AND METHOD - A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed. | 03-20-2014 |
20140077856 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR SELF-HEATING AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device comprises a first clock signal source, arranged to provide at least one first clock signal; a second clock signal source, arranged to provide at least one second clock signal different from the at least one first clock signal; and a plurality of sequential logic cells, at least one of the plurality connected to receive, in a first mode, the at least one first clock signal or at least one clock signal derived from the at least one first clock signal, and to receive, in a second mode, the at least one second clock signal or at least one clock signal derived from the at least one second clock signal; wherein in the second mode the at least one second clock signal is adapted to the at least one of the plurality of sequential logic cells to generate in at least a portion of the integrated circuit device a current consumption when the at least one first clock signal is not a toggling signal. | 03-20-2014 |
20140085758 | INTEGRATED CIRCUIT DEVICE AND METHOD OF ENABLING THERMAL REGULATION WITHIN AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device comprising at least one electrostatic discharge (ESD) clamp device. The at least one ESD clamp device comprises a first channel input, a second channel input, and a control input arranged to receive a control signal. The at least one ESD clamp device is arranged to selectively operate in a conductive state in which the at least one ESD clamp device permits current to flow between the first and second channel inputs thereof based at least partly on the received control signal. The integrated circuit device further comprises at least one biasing module. The at least one biasing module comprises at least one output operably coupled to the control input of the at least one ESD clamp device and at least one input arranged to receive a thermal regulation signal. The at least one biasing module being arranged to apply a bias to the control signal for the at least one ESD clamp device based at least partly on the received thermal regulation signal. | 03-27-2014 |
20140097884 | INTEGRATED CIRCUIT DEVICE AND METHOD OF IMPLEMENTING POWER GATING WITHIN AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node. | 04-10-2014 |
20140115358 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR CONTROLLING AN OPERATING MODE OF AN ON-DIE MEMORY - An integrated circuit device comprising at least one instruction processing module, at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further, lower-power mode, and at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further, lower-power modes. | 04-24-2014 |
20140176220 | INTEGRATED CIRCUIT DEVICE, VOLTAGE REGULATOR MODULE AND METHOD FOR COMPENSATING A VOLTAGE SIGNAL - An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current. | 06-26-2014 |
20150084417 | ELECTRONIC DEVICE AND METHOD FOR OPERATING A POWER SWITCH - An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described. | 03-26-2015 |
20150095525 | INTEGRATED CIRCUIT COMPRISING AN IO BUFFER DRIVER AND METHOD THEREFOR - An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal. | 04-02-2015 |
20150145556 | IO DRIVER IMPEDANCE CALIBRATION - An IO driver for an integrated circuit and a method for calibrating such an IO driver are provided. The IO driver comprises a plurality of IO driver cells, a plurality of IO partial driver cells and an external resistor. The IO driver cells control IO operations for a corresponding plurality of data channels of the integrated circuit. The IO partial driver cells are coupled to respective cells of the plurality of IO driver cells. The external resistor provides a reference impedance. The reference partial driver cell is coupled to the external resistor and is arranged to determine the reference impedance and to provide information depending on the reference impedance to the IO partial driver cells. The IO partial driver cells are arranged to calibrate the respective IO driver cells based on the provided information. | 05-28-2015 |
20150162818 | SYSTEM ON A CHIP, APPARATUS AND METHOD FOR VOLTAGE RIPPLE REDUCTION ON A POWER SUPPLY LINE OF AN INTEGRATED CIRCUIT DEVICE OPERABLE IN AT LEAST TWO MODES - An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. The clamp control unit is arranged to connect at least one of the one or more clamping devices to the power supply line when receiving the mode change signal. | 06-11-2015 |
20150180475 | INPUT/OUTPUT DRIVER CIRCUIT, INTEGRATED CIRCUIT AND METHOD THEREFOR - An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period. | 06-25-2015 |
20150181435 | SYSTEMS AND METHODS FOR SECURING NEAR FIELD COMMUNICATIONS - Systems and methods to secure near field communications (NFC) are disclosed. An NFC polling device may detect a change in voltage when attempting to communicate with another NFC device and based at least in part on the magnitude of the change in voltage if there is an attempted hacking and/or snooping event. The NFC polling device may further identify the number of modulation voltage levels detected and determine if there is an attempted hacking event based on the number of modulation voltage levels detected. | 06-25-2015 |
20150204917 | System and method for on-die voltage difference measurement on a pass device, and integrated circuit - A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal. | 07-23-2015 |