Patent application number | Description | Published |
20140081708 | LATENT SEMANTIC ENGINEERING PROCESSES, DEVICES, AND METHODS - Latent Semantic Engineering processes, devices, and methods match (aspirational, emotional, functional, physical) Latent Semantic Engineering semantic space user needs to (aspirational, emotional, functional, physical) Latent Semantic Engineering semantic space designs. Latent Semantic Engineering processes, devices, and methods thereby match user needs to designs, increase matching accuracy, and increase product quality, customer satisfaction, and product success. | 03-20-2014 |
20140125469 | REALISTIC TACTILE HAPTIC FEEDBACK DEVICE AND REALISTIC TACTILE HAPTIC FEEDBACK METHOD THEREOF - A realistic tactile haptic device comprising a first vibration sensor, a digital controller, an actuator, and a similar or identical second vibration sensor, and a realistic tactile haptic feedback method thereof, provides users with realistic tactile haptic feedback that is similar to or the same as real tactile haptic feedback which users would experience by touching real objects. | 05-08-2014 |
Patent application number | Description | Published |
20120140396 | TABLET PC COVER WITH INTEGRAL KEYBOARD - A cover for a tablet PC with an integral keyboard provides two outer covering faces and a resilient mounting frame fixing a tablet PC therein, hinged on a keyboard component. By hinging partway along one outer covering face, the mounting frame can assume a wide variety of angles. The keyboard component has embedded within its underside a ferromagnetic member attracted by an embedded metal strip in the other covering face, fixing the keyboard and mounting frame at any desired angle. The resilient mounting frame has an ejection assembly opposite the hinging of the resilient mounting frame and keyboard component, allowing one-handed release of the tablet PC, and an embedded implant corresponding to and detectable by a configurable circuit board encased in the keyboard component. | 06-07-2012 |
20120327044 | STYLUS ASSEMBLY FOR A CAPACITIVE TOUCH SCREEN - A stylus assembly for a capacitive touch screen provides input via conventional handwriting action. A stylus is attached at a contact end to a disc providing ample capacitive proximity with the touch screen. A layer of capacitive material is embedded within the disc, and may be formed with a distinct shape, layout, or outline to provide a uniquely recognizable capacitive signature. The stylus terminates at the contact end in a received portion, attached to the disc by a receiving portion formed thereon. Free rotation of the received portion within the receiving portion accepts positioning of the stylus body at any angle with no degradation of capacitive proximity, allowing natural handwriting action. The receiving portion can be formed with sufficient flexibility to allow disengagement and re-engagement thereof, enabling simple and low-cost replacement of the disc. | 12-27-2012 |
Patent application number | Description | Published |
20080259334 | MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 10-23-2008 |
20090116014 | Determining Overlay Error Using an In-chip Overlay Target - Overlay error between two layers on a substrate is measured using an image of an overlay target in an active area of a substrate. The overlay target may be active features, e.g., structures that cause the device to function as desired when manufacturing is complete. The active features may be permanent structures or non-permanent structures, such as photoresist, that are used define the permanent structures during manufacturing. The image of the overlay target is analyzed by measuring the light intensity along one or more scan lines and calculating a symmetry values for the scan lines. Using the symmetry values, the overlay error can be determined. | 05-07-2009 |
20090296075 | Imaging Diffraction Based Overlay - An overlay error is determined using a diffraction based overlay target by generating a number of narrow band illumination beams that illuminate the overlay target. Each beam has a different range of wavelengths. Images of the overlay target are produced for each different range of wavelengths. An intensity value is then determined for each range of wavelengths. In an embodiment in which the overlay target includes a plurality of measurement pads, which may be illuminated and imaged simultaneously, an intensity value for each measurement pad in each image is determined. The intensity value may be determined statistically, such as by summing, finding the mean or median of the intensity values of pixels in the image. Spectra is then constructed using the determined intensity value, e.g., for each measurement pad. Using the constructed spectra, the overlay error may then be determined. | 12-03-2009 |
20110058170 | MULTI LAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 03-10-2011 |
20110069314 | MULTILAYER ALIGNMENT AND OVERLAY TARGET AND MEASUREMENT METHOD - A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields. | 03-24-2011 |
Patent application number | Description | Published |
20090243679 | Semi-Digital Delay Locked Loop Circuit and Method - A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal. | 10-01-2009 |
20110006820 | Dual Phase-Locked Loop Circuit and Method for Controlling the Same - A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency. | 01-13-2011 |
20110032978 | Receiver and Method for Adjusting Adaptive Equalizer of Receiver - A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals. | 02-10-2011 |
20110128057 | Delay Locked Loop and Associated Method - A delay locked loop includes a pulse generator, a delay unit, a phase detector and a control unit. The pulse generator generates a pulse signal and a determination signal according to an input clock signal. The delay unit delays the pulse signal according to a digital control signal to generate a delayed pulse signal. The phase detector detects a time delay of the delayed pulse signal according to the determination signal to generate a detection result. The control unit generates a digital control signal according to the detection result to control the delayed pulse signal by a delay amount. | 06-02-2011 |
20110128061 | Phase Generating Apparatus and Method Thereof - A phase generating apparatus generates an output clock having a desired phase according to a digital signal. The apparatus includes a phase selecting unit and a phase generating unit. The phase selecting unit selects one of a plurality of input clocks according to a portion of bits of the digital signal to generate a reference clock. Each of the input clocks respectively has a difference phase. The phase selecting unit divides the frequency of the reference clock, and selectively delays the frequency-divided reference clock according to another portion of bits of the digital signal to generate the output clock. | 06-02-2011 |
20110131354 | Apparatus and Method of Generating Universal Memory I/O - A universal memory I/O generating apparatus includes a defining module, a retrieving module, a generating module, and a layout module. The defining module defines a mapping table according to a pin configuration of a plurality of I/Os. The mapping table includes corresponding relationships between the plurality of IOs and a plurality of memory functions. The retrieving module retrieves control information corresponding to the mapping table from candidate information, which is associated with the corresponding relationships between the plurality of I/Os and the plurality of memory functions. The generating module generates a hardware description language (HDL) file according to the control information. The layout module programs the plurality of I/Os according to the HDL file, so that each of the I/Os can correspond to its corresponding memory function. | 06-02-2011 |
20140002731 | APPARATUS AND METHOD FOR INCREASING PIXEL RESOLUTION OF IMAGE USING COHERENT SAMPLING | 01-02-2014 |