Patent application number | Description | Published |
20100264497 | Multiple Vt Field-Effect Transistor Devices - Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. | 10-21-2010 |
20110063019 | DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR - A dual dielectric tri-gate field effect transistor, a method of fabricating a dual dielectric tri-gate field effect transistor, and a method of operating a dual dielectric tri-gate effect transistor are disclosed. In one embodiment, the dual dielectric tri-gate transistor comprises a substrate, an insulating layer on the substrate, and at least one semiconductor fin. A first dielectric having a first dielectric constant extends over sidewalls of the fin, and a metal layer extends over the first dielectric, and a second dielectric having a second dielectric constant is on a top surface of the fin. A gate electrode extends over the fin and the first and second dielectrics. The gate electrode and the first dielectric layer form first and second gates having a threshold voltage Vt | 03-17-2011 |
20110065244 | ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE - A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region. | 03-17-2011 |
20110073958 | ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL - A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric. | 03-31-2011 |
20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
20110133161 | Omega Shaped Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region. | 06-09-2011 |
20110133162 | Gate-All-Around Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. | 06-09-2011 |
20110133164 | Omega Shaped Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region. | 06-09-2011 |
20110133165 | SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions. | 06-09-2011 |
20110133166 | NANOWIRE FET HAVING INDUCED RADIAL STRAIN - A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire. | 06-09-2011 |
20110133167 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - A method for forming an integrated circuit, the method includes forming a first nanowire suspended above an insulator substrate, the first nanowire attached to a first silicon on insulator (SOI) pad region and a second SOI pad region that are disposed on the insulator substrate, a second nanowire disposed on the insulator substrate attached to a third SOI pad region and a fourth SOI pad region that are disposed on the insulator substrate, and a SOI slab region that is disposed on the insulator substrate, and forming a first gate surrounding a portion of the first nanowire, a second gate on a portion of the second nanowire, and a third gate on a portion of the SOI slab region. | 06-09-2011 |
20110133169 | Gate-All-Around Nanowire Tunnel Field Effect Transistors - A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region. | 06-09-2011 |
20110168982 | NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A method for forming a nanowire tunnel device includes forming a nanowire suspended by a first pad region and a second pad region over a semiconductor substrate, forming a gate structure around a channel region of the nanowire, implanting a first type of ions at a first oblique angle in a first portion of the nanowire and the first pad region, and implanting a second type of ions at a second oblique angle in a second portion of the nanowire and the second pad region. | 07-14-2011 |
20110169051 | Structure for Use in Fabrication of PiN Heterojunction TFET - A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region. | 07-14-2011 |
20110191737 | GENERATION OF ASYMMETRIC CIRCUIT DEVICES - A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels. | 08-04-2011 |
20120286242 | NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES - A nanowire tunnel device includes a nanowire suspended above a semiconductor substrate by a first pad region and a second pad region, the nanowire having a channel portion surrounded by a gate structure disposed circumferentially around the nanowire, an n-type doped region including a first portion of the nanowire adjacent to the channel portion, and a p-type doped region including a second portion of the nanowire adjacent to the channel portion. | 11-15-2012 |
20120292678 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 11-22-2012 |
20120298963 | STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET - A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region. | 11-29-2012 |
20120319084 | PLANAR AND NANOWIRE FIELD EFFECT TRANSISTORS - An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer. | 12-20-2012 |
20140073106 | LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY - A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process. | 03-13-2014 |
20140170829 | LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY - A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process. | 06-19-2014 |