Patent application number | Description | Published |
20100048012 | Method for fabricating nonvolatile memory device - Provided is a method for fabricating a nonvolatile memory device capable of improving charge retention characteristics. The method for fabricating a nonvolatile memory device includes forming a charge trapping layer with a memory region and a charge blocking region on a semiconductor substrate, and trapping charges in the charge blocking region of the charge trapping layer. | 02-25-2010 |
20100123181 | NONVOLATILE MEMORY DEVICES INCLUDING MULTIPLE CHARGE TRAPPING LAYERS - A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer. | 05-20-2010 |
20100133599 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 06-03-2010 |
20100213536 | Nonvolatile Memory Device and Method of Forming the Same - A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region. | 08-26-2010 |
20110001181 | Nonvolatile Memory Devices - Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer. | 01-06-2011 |
20110147825 | NONVOLATILE MEMORY DEVICES INCLUDING DEEP AND HIGH DENSITY TRAPPING LAYERS - A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the gate electrode and the substrate, the charge trapping layer having trap sites configured to trap charges; a charge tunneling layer between the trapping layer and the semiconductor substrate; and a charge blocking layer between the gate electrode and the trapping layer. The charge trapping layer comprises a deep trapping layer having a plurality of energy barriers and a high density trapping layer having a trap site density higher than a trap site density of the deep trapping layer. | 06-23-2011 |
20110292731 | Three-Dimensional Non-Volatile Memory Devices Having Highly Integrated String Selection and Sense Amplifier Circuits Therein - Nonvolatile memory devices include an electrically insulating layer on a semiconductor substrate and a NAND-type string of nonvolatile memory cells on an upper surface of the electrically insulating layer. The NAND-type string of nonvolatile memory cells includes a plurality of vertically-stacked nonvolatile memory cell sub-strings disposed at side-by-side locations on the electrically insulating layer. A string selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. A ground selection transistor is provided, which includes a gate electrode extending between the electrically insulating layer and the semiconductor substrate and source and drain regions in the semiconductor substrate. | 12-01-2011 |
20130277720 | FIN FIELD EFFECT TRANSISTORS - Field effect transistors include a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode. | 10-24-2013 |
20140015128 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 01-16-2014 |
20150068948 | WAFER LOADERS HAVING BUFFER ZONES - Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone. | 03-12-2015 |