Patent application number | Description | Published |
20080235461 | Technique and apparatus for combining partial write transactions - A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available. | 09-25-2008 |
20080320192 | FRONT SIDE BUS PERFORMANCE USING AN EARLY DEFER-REPLY MECHANISM - Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving the performance of a front side bus using an early defer-reply mechanism. In some embodiments, an integrated circuit receives a memory read request and accesses memory to obtain read data responsive to receiving the memory read request. The integrated circuit may initiate a defer-reply transaction corresponding to the memory read request N front side bus (FSB) clocks prior to receiving the read data from the memory. | 12-25-2008 |
20090031058 | Methods and Apparatuses for Flushing Write-Combined Data From A Buffer - Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device. | 01-29-2009 |
20100081406 | Dynamic squelch detection power control - In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed. | 04-01-2010 |
20110060931 | POWER MEASUREMENT TECHNIQUES OF A SYSTEM-ON-CHIP (SOC) - A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts. | 03-10-2011 |
20110296222 | DYNAMIC AND IDLE POWER REDUCTION SEQUENCE USING RECOMBINANT CLOCK AND POWER GATING - Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed. | 12-01-2011 |
20120036291 | STREAM PRIORITY - A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction. | 02-09-2012 |
20120042106 | STREAM PRIORITY - A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction. | 02-16-2012 |
20120166909 | METHOD AND APPARATUS FOR INCREASING DATA RELIABILITY FOR RAID OPERATIONS - A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations. | 06-28-2012 |
20130007573 | EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC - Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic. | 01-03-2013 |
20140082451 | EFFICIENT AND SCALABLE CYCLIC REDUNDANCY CHECK CIRCUIT USING GALOIS-FIELD ARITHMETIC - Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic. | 03-20-2014 |
20140189212 | PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. | 07-03-2014 |