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| 20080310418 | OUTPUT QUEUED SWITCH WITH A PARALLEL SHARED MEMORY, AND METHOD OF OPERATING SAME - A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node. | 12-18-2008 |
| 20090034517 | ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER - The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position. | 02-05-2009 |
| 20110013643 | ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER - The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position. | 01-20-2011 |
| 20110085553 | OUTPUT QUEUED SWITCH WITH A PARALLEL SHARED MEMORY, AND METHOD OF OPERATING SAME - A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node. | 04-14-2011 |
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| 20090247567 | BENZOPYRAN AND BENZOXEPIN PI3K INHIBITOR COMPOUNDS AND METHODS OF USE - Benzopyran and benzoxepin compounds of Formulas I and II, and including stereoisomers, geometric isomers, tautomers, solvates, metabolites and pharmaceutically acceptable salts thereof, are useful for inhibiting lipid kinases including p110 alpha and other isoforms of PI3K, and for treating disorders such as cancer mediated by lipid kinases. Methods of using compounds of Formulas I and II for in vitro, in situ, and in vivo diagnosis, prevention or treatment of such disorders in mammalian cells, or associated pathological conditions, are disclosed. | 10-01-2009 |
| 20110130363 | BENZOPYRAN AND BENZOXEPIN PI3K INHIBITOR COMPOUNDS AND METHODS OF USE - Benzopyran and benzoxepin compounds of Formulas I and II, and including stereoisomers, geometric isomers, tautomers, solvates, metabolites and pharmaceutically acceptable salts thereof, are useful for inhibiting lipid kinases including p110 alpha and other isoforms of PI3K, and for treating disorders such as cancer mediated by lipid kinases. Methods of using compounds of Formulas I and II for in vitro, in situ, and in vivo diagnosis, prevention or treatment of such disorders in mammalian cells, or associated pathological conditions, are disclosed. | 06-02-2011 |
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| 20090150654 | FUSED MULTIPLY-ADD FUNCTIONAL UNIT - A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area. | 06-11-2009 |
| 20110072243 | Unified Collector Structure for Multi-Bank Register File - One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles. | 03-24-2011 |
| 20110072438 | FAST MAPPING TABLE REGISTER FILE ALLOCATION ALGORITHM FOR SIMT PROCESSORS - One embodiment of the present invention sets forth a technique for allocating register file entries included in a register file to a thread group. A request to allocate a number of register file entries to the thread group is received. A required number of mapping table entries included in a register file mapping table (RFMT) is determined based on the request, where each mapping table entry included in the RFMT is associated with a different plurality of register file entries included in the register file. The RFMT is parsed to locate an available mapping table entry in the RFMT for each of the required mapping table entries. For each available mapping table entry, a register file pointer is associated with an address that corresponds to a first register file entry in the plurality of register file entries associated with the available mapping table entry. | 03-24-2011 |
| 20110078417 | COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS - One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. | 03-31-2011 |
| 20110078427 | TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT - A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment. | 03-31-2011 |
| 20110078690 | Opcode-Specified Predicatable Warp Post-Synchronization - One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that includes at least one set-synchronization instruction and at least one instruction that includes a synchronization command, and determining an active mask that indicates which threads in a plurality of threads are active and which threads in the plurality of threads are disabled. For each instruction included in the plurality of instructions, the instruction is transmitted to each of the active threads included in the plurality of threads. If the instruction is a set-synchronization instruction, then a synchronization token, the active mask and the synchronization point is each pushed onto a stack. Or, if the instruction is a predicated instruction that includes a synchronization command, then each active thread that executes the predicated instruction is monitored to determine when the active mask has been updated to indicate that each active thread, after executing the predicated instruction, has been disabled. | 03-31-2011 |
| 20110081100 | USING A PIXEL OFFSET FOR EVALUATING A PLANE EQUATION - One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives. | 04-07-2011 |
| 20110252204 | SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL REQUESTS - A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once. | 10-13-2011 |
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| 20100232309 | METHODS AND SYSTEMS FOR DYNAMIC CALL BLOCKING IN WIMAX IDLE MODE - Certain embodiments of the present disclosure present methods and apparatuses that enable a mobile station (MS) to selectively reject downlink (DL) data during idle mode. The MS may determine whether to reject the pending DL data based on information about the data. This information may be provided by a base station (BS) that is part of the access service network (ASN) that is retaining the DL data. The information provided by the BS may, for instance, include service flow information related to the pending DL data. In certain embodiments, the information may include one or more internet protocol (IP) packets that are part of the pending DL data. | 09-16-2010 |
| 20100311391 | METHOD AND SYSTEM FOR PERFORMING MULTI-STAGE VIRTUAL SIM PROVISIONING AND SETUP ON MOBILE DEVICES - A system and method for provisioning a mobile device with user preferences and settings. The user preferences and settings may be default preferences and settings selected by the various applications loaded onto the mobile device or previously user preferences and settings selected by a user. User selected preferences and settings may be stored in a remote server memory. The preferences and settings may be retrieved by new mobile device. The preferences and settings stored in the remote server memory may contain triggers which initiate a connection with various third party servers. In response to the trigger, various third party servers may transmit further instructions to the mobile device which allows the mobile device to complete the restoration of the user's preferences and settings. | 12-09-2010 |
| 20100311402 | METHOD AND APPARATUS FOR PERFORMING SOFT SWITCH OF VIRTUAL SIM SERVICE CONTRACTS - A system and method for providing updated rules governing the switching of enabled provisioning data supporting a wireless service contract. A mobile device may be initially programmed with a profile data table and priority list index data table to automatically enable provisioning data supporting one of the plurality of service providers stored in a VSIM internal memory unit to conduct a wireless communication when certain operational parameter values are satisfied. The profile data table and priority list index data table may be automatically updated in response to a variety of triggers. The profile data table and priority list index data table may be stored remotely. Operational parameters regarding each call request are collected and transmitted to a remote service contract selection server. The selection of an optimal service provider account may be made remotely in the service contract selection server and transmitted back to the mobile device. | 12-09-2010 |
| 20100311404 | METHOD AND APPARATUS FOR UPDATING RULES GOVERNING THE SWITCHING OF VIRTUAL SIM SERVICE CONTRACTS - A system and method for providing updated rules governing the switching of enabled provisioning data supporting a wireless service contract. A mobile device may be initially programmed with a profile data table and priority list index data table to automatically enable provisioning data supporting one of the plurality of service providers stored in a VSIM internal memory unit to conduct a wireless communication when certain operational parameter values are satisfied. The profile data table and priority list index data table may be automatically updated in response to a variety of triggers. | 12-09-2010 |
| 20100311418 | METHOD AND APPARATUS FOR SWITCHING VIRTUAL SIM SERVICE CONTRACTS WHEN ROAMING - A system and method store provisioning data supporting a plurality of service providers in a VSIM internal memory unit of a mobile device. The mobile device may automatically enable provisioning data supporting one of the plurality of service providers stored in the VSIM internal memory unit to conduct a wireless communication so as to avoid roaming fees. | 12-09-2010 |
| 20100311444 | METHOD AND APPARATUS FOR SWITCHING VIRTUAL SIM SERVICE CONTRACTS BASED UPON A USER PROFILE - A system and method store provisioning data supporting a plurality of service providers in a VSIM internal memory unit of a mobile device. A user may specify a user profile to automatically enable provisioning data supporting one of the plurality of service providers stored in the VSIM internal memory unit to conduct a wireless communication when certain criteria values are satisfied. The automatic enabling of provisioning data may be determined based upon mobile device location, communication usage request and/or time and date. | 12-09-2010 |
| 20100311468 | VIRTUAL SIM CARD FOR MOBILE HANDSETS - A system and method store provisioning data supporting a plurality of service providers in a VSIM internal memory unit of a mobile device. A user may selectively enable provisioning data supporting one of the plurality of service providers stored in the VSIM internal memory unit to conduct a wireless communication. An embodiment permits backing up, retrieving and restoring personal data in the VSIM internal memory unit using a remote database. Another embodiment allows a mobile device to select an optimal service provider to conduct a wireless communication. The optimal service provider may be determined based upon mobile device location, communication usage request and/or time and date. | 12-09-2010 |
