| Patent application number | Description | Published |
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| 20090157989 | Distributing Metadata Across Multiple Different Disruption Regions Within an Asymmetric Memory System - Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond. | 06-18-2009 |
| 20100325383 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 12-23-2010 |
| 20110022788 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 01-27-2011 |
| 20110167205 | SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY - A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component. | 07-07-2011 |
| 20110173371 | WRITING TO ASYMMETRIC MEMORY - A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address. | 07-14-2011 |
| 20120198140 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 08-02-2012 |
| 20120198141 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 08-02-2012 |
| Patent application number | Description | Published |
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| 20090013367 | Methods and Apparatus for Efficient Network Information Acquisition Over a DVB Network - Methods and apparatus for efficient network information acquisition over a DVB network. In an aspect, a method includes identifying an IP/MAC platform, acquiring network information table (NIT) information in a transport stream being transmitted on a forward link frequency, acquiring IP/MAC network table (INT) information associated with the IP/MAC platform based on the NIT information, creating a network list that identifies all networks referred to by all stream location descriptors associated with the selected IP/MAC platform based on the INT information, and acquiring network information for all the networks in the network list. In an aspect, an apparatus includes means for identifying an IP/MAC platform, means for acquiring NIT information, and means for acquiring INT information, means for creating a network list that identifies networks associated with the selected IP/MAC platform, and means for acquiring network information for all the networks in the network list. | 01-08-2009 |
| 20090019499 | Methods and Apparatus for Improved Program Acquisition for Use with MPEG-2 Based Systems - Methods and apparatus for improved program acquisition for use with MPEG-2 based systems. In an aspect, a method includes receiving a program association table (PAT) associated with an MPEG-2 transport stream, and identifying program map tables (PMTs) included in the PAT. The method also includes caching the PMTs, receiving a request to present a program, determining if a PMT associated with the program has been cached, and acquiring the selected program using information from the cached PMT. An apparatus includes means for receiving a PAT associated with an MPEG-2 transport stream and means for identifying PMTs included in the PAT. The apparatus also includes means for caching the PMTs, means for receiving a request to present a program, means for determining if a PMT associated with the program has been cached, and means for acquiring the selected program using information from the cached PMT. | 01-15-2009 |
| 20090077585 | METHOD AND APPARATUS TO ENABLE FAST CHANNEL SWITCHING WITH LIMITED DVB RECEIVER MEMORY - An apparatus and method for channel switching comprising encapsulating a plurality of IP datagrams associated with a plurality of real time audio/visual (A/V) streams or a plurality of file objects onto a plurality of MPE sections; inserting the plurality of MPE sections into one of a plurality of elementary streams; and multiplexing the plurality of elementary streams associated with the plurality of real time A/V streams or the plurality of file objects into a plurality of non-consecutive bursts, wherein the plurality of elementary streams are adjacent in a channel line-up. In one aspect, the plurality of non-consecutive bursts is transmitted to a DVB-H receiver with a limited memory size for enabling fast channel switching. In one aspect, the channel line-up is presented in an electronic service guide (ESG). | 03-19-2009 |
| 20090080512 | METHOD AND APPARATUS FOR RECEIVING MULTIPLE SIMULTANEOUS STREAM BURSTS WITH LIMITED DVB RECEIVER MEMORY - An apparatus and method for receiving multiple simultaneous stream bursts comprising determining if a frame size is smaller than a size of an available memory; determining if a priority of a first packet is lower than a priority of a second packet, wherein the frame size is of a frame for the second packet; requesting to abort processing the first packet and to de-assign the available memory from the first packet if the priority of the first packet is lower than the priority of the second packet; waiting for the size of the available memory to become equal or greater than the frame size if the priority of the first packet is not lower than the priority of the second packet; and assigning the available memory to the frame for the second packet. | 03-26-2009 |
