Sinangil
Mahmut E. Sinangil, Medford, MA US
Patent application number | Description | Published |
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20150016183 | SENSE AMPLIFIER WITH TRANSISTOR THRESHOLD COMPENSATION - One embodiment provides, in a sense amplifier for an electronic memory array in which a selected memory cell drives a developing voltage differential according to a logic state of the memory cell, a method to store the logic state. The method includes poising source voltages of first and second transistors at levels offset, respectively, by threshold voltages of the first and second transistors. The method also includes applying the voltage differential between a gate of the first transistor and a gate of the second transistor, the first and second transistors configured to oppose each other in a cross-coupled inverter stage of the sense amplifier. | 01-15-2015 |
Mahmut Ersin Sinangil, Medford, MA US
Patent application number | Description | Published |
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20140160871 | SYSTEM AND METHOD FOR PERFORMING SRAM WRITE ASSIST - A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell. | 06-12-2014 |
20140204687 | SYSTEM AND METHOD FOR PERFORMING ADDRESS-BASED SRAM ACCESS ASSISTS - A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access. | 07-24-2014 |
Mahmut Ersin Sinangil, Westford, MA US
Patent application number | Description | Published |
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20150199223 | APPROACH TO PREDICTIVE VERIFICATION OF WRITE INTEGRITY IN A MEMORY DRIVER - A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance. | 07-16-2015 |