Patent application number | Description | Published |
20100096719 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are isotropically etched to remove the etch mask pattern from the first mask structure while maintaining at least a portion of the etch mask pattern on the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region using the portion of the etch mask pattern on the second mask structure as a mask to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. The feature layer may be patterned using the first mask pattern as a mask to define a first feature on the first region, and using the second mask pattern as a mask to define a second feature on the second region having a greater width than the first feature. | 04-22-2010 |
20120252185 | METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES - A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region. | 10-04-2012 |
20130264649 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including an active region and a field region, first gate structures disposed on the active region, first air gaps disposed between the first gate structures, second gate structures disposed on the field region, second air gaps disposed between the second gate structures, and an interlayer insulating layer disposed on the first gate structures, the first air gaps, the second gate structures, and the second air gaps. A lowermost level of the second air gaps is lower than a lowermost level of the first gate structures. | 10-10-2013 |
20150325478 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines. | 11-12-2015 |
Patent application number | Description | Published |
20090185421 | Charge-Trap Flash Memory Device with Reduced Erasure Stress and Related Programming and Erasing Methods Thereof - Operation methods of charge-trap flash memory devices having an unused memory cell for data storage and a normal memory cell used for data storage are discussed. The operation method may include selecting the unused memory cell, and programming the unused memory cell to have a predetermined threshold voltage. The charge-trap flash memory device may thus be provided with improved reliability by interrupting erasure stress to unused memory cells. | 07-23-2009 |
20100002516 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 01-07-2010 |
20100221886 | Methods of Forming Charge-Trap Type Non-Volatile Memory Devices - Methods of forming a non-volatile memory device may include forming a tunnel insulating layer on a semiconductor substrate and forming a charge-trap layer on the tunnel insulating layer. A trench may then be formed extending through the tunnel insulating layer and the charge-trap layer and into the semiconductor substrate so that portions of the charge-trap layer and the tunnel insulating layers remain on opposite sides of the trench. A device isolation layer may be formed in the trench, and a blocking insulating layer may be formed on the device isolation layer and on remaining portions of the charge-trap layer. A gate electrode may be formed on the blocking insulating layer, and the blocking insulating layer and remaining portions of the charge-trap layer may be patterned to provide a blocking insulating pattern and a charge-trap pattern between the gate electrode and the semiconductor substrate. | 09-02-2010 |
20110117722 | Semiconductor Device With Charge Storage Pattern And Method For Fabricating The Same - A semiconductor device (e.g., a non-volatile memory device) with improved data retention characteristics includes active regions that protrude above a top surface of a device isolation region. A tunneling insulating layer is formed on the active regions. Charge storage patterns (e.g., charge trap patterns) are formed so as to be spaced apart from each other. A blocking insulating layer and a gate are formed on the charge storage patterns. | 05-19-2011 |
20110266607 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 11-03-2011 |
Patent application number | Description | Published |
20130331377 | DIAMINOPYRIMIDINE DERIVATIVES AND PROCESSES FOR THE PREPARATION THEREOF - The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT | 12-12-2013 |
20130338179 | DIAMINOPYRIMIDINE DERIVATIVES AND PROCESSES FOR THE PREPARATION THEREOF - The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT | 12-19-2013 |
20150274700 | DIAMINOPYRIMIDINE DERIVATIVES AND PROCESSES FOR THE PREPARATION THEREOF - The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT | 10-01-2015 |
20160090374 | BICYCLIC DERIVATIVE CONTAINING PYRIMIDINE RING, AND PREPARATION METHOD THEREFOR - The present invention provides: a bicyclic derivative comprising a pyrimidine ring, or a pharmaceutically acceptable salt thereof; a preparation method therefor, a pharmaceutical composition comprising the same; and a use therefor. According to the present invention, the bicyclic compound derivative comprising a pyrimidine ring, or a pharmaceutically acceptable salt thereof acts as a 5-HT | 03-31-2016 |
Patent application number | Description | Published |
20110170336 | DRAM Device and Manufacturing Method Thereof - The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size. | 07-14-2011 |
20120134195 | Memory Device and Manufacturing Method Thereof - The present invention relates to a memory device having | 05-31-2012 |
20120236620 | Nonvolatile Memory Device and Manufacturing Method Thereof - The present invention relates to a nonvolatile memory device and a manufacturing method thereof, the device comprising a plurality of word lines; a plurality of bit lines perpendicular to the word lines; and a plurality of memory cells including a transistor with a source connected to a source line, a gate, and a drain connected to a memory element, with the other end of the memory element connected to the bit lines. Between memory cells adjacent along a bit line, a gate terminal in a groove between the memory cells connects the gates in the memory cells to a word line. Memory cells adjacent along a word line are connected to one bit line contact point, and memory cells sharing a gate terminal are connected to different bit lines. Bit lines are disposed at the upper portion and source lines at the lower end of the memory cell. | 09-20-2012 |
Patent application number | Description | Published |
20140160839 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140162429 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140361240 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 12-11-2014 |
20160071955 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 03-10-2016 |
20160079390 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND METHOD OF MANUFACTURING THE SAME - A semiconductor integrated circuit apparatus and a method of manufacturing the same are provided. The semiconductor integrated circuit apparatus includes a semiconductor substrate having an active island, a gate buried in a predetermined portion of the active island, a source and a drain formed at both sides of the gate, and a current blocking layer formed in the active island corresponding to a lower portion of the drain. When current flows in from the drain, the current blocking layer is configured to discharge the current into the inside of the semiconductor substrate through a lower portion of the source. | 03-17-2016 |
Patent application number | Description | Published |
20100090040 | Pulverizer for food waste treatment apparatus - The present invention provides a pulverizer of a food waste treatment apparatus. The pulverizer of the present invention includes a main body, a pulverizing screw and an exhaust channel unit. The main body has a hollow space therein. The pulverizing screw includes a rotating shaft which is installed in the main body so as to be rotatable, and at least one drive blade which extends from the rotating shaft. The exhaust channel unit has an annular shape and is coupled to the upper end of the main body. An intake hole and an exhaust hole are formed through the outer surface of the exhaust channel unit. Furthermore, a cover may be removably coupled to the upper end of the exhaust channel unit. | 04-15-2010 |
20100090046 | Pulverizing screw, pulverizing casing and pulverizer for food waste treatment apparatus having the same - The present invention provides a pulverizing screw, a pulverizing casing and a pulverizer having the same. The pulverizing screw includes a rotating shaft and a drive blade which extends from the rotating shaft in a spiral shape. The drive blade rotates in the pulverizing casing in such a manner as to maintain a predetermined distance between the drive blade and the inner surface of the pulverizing casing to prevent the drive blade from being impeded by the inner surface of the pulverizing casing. The drive blade extends from a first end of the rotating shaft in a spiral shape surrounding the rotating shaft in a clockwise or counterclockwise direction and is connected to a second end of the rotating shaft. The pulverizing casing comprises a spherical body having a space therein. The pulverizing screw is installed in the spherical body so as to be rotatable. | 04-15-2010 |
20120217332 | PULVERIZING SCREW, PULVERIZING CASING AND PULVERIZER FOR FOOD WASTE TREATMENT APPARATUS HAVING THE SAME - The present invention provides a pulverizing screw, a pulverizing casing and a pulverizer having the same. The pulverizing screw includes a rotating shaft and a drive blade which extends from the rotating shaft in a spiral shape. The drive blade rotates in the pulverizing casing in such a manner as to maintain a predetermined distance between the drive blade and the inner surface of the pulverizing casing to prevent the drive blade from being impeded by the inner surface of the pulverizing casing. The drive blade extends from a first end of the rotating shaft in a spiral shape surrounding the rotating shaft in a clockwise or counterclockwise direction and is connected to a second end of the rotating shaft. The pulverizing casing comprises a spherical body having a space therein. The pulverizing screw is installed in the spherical body so as to be rotatable. | 08-30-2012 |
Patent application number | Description | Published |
20130027472 | APPARATUS FOR EJECTING DROPLETS - Disclosed herein is an ejecting apparatus including: an upper bezel which includes an inlet through which ejectable fluid flows in from an external source, a channel which fluidly communicates with the inlet and through which the ejectable fluid flows, and an upper mounting portion which fluidly communicates with the channel and is opened downwardly; a lower bezel which includes a lower mounting portion which is opened upwardly to correspond to the upper mounting portion, and a nozzle slit which fluidly communicates with the lower mounting portion to eject the ejectable fluid to an outside, the lower bezel being fastened to the upper bezel, and a nozzle chip which is interposed between the upper mounting portion and the lower mounting portion to receive the ejectable fluid from the channel and discharge the ejectable fluid into the nozzle slit by being driven by an actuator. | 01-31-2013 |
20130147595 | COIL PARTS - Disclosed herein are coil parts including: a lower magnetic substance; a primary coil pattern disposed on the lower magnetic substance; a first complex layer for covering the primary coil pattern; a secondary coil pattern correspondingly disposed on an upper side of the primary coil pattern; a second complex layer for covering the secondary coil pattern; and an insulation layer disposed between the primary coil pattern and the secondary coil pattern and blocking an electrical connection between the primary coil pattern and the secondary coil pattern. The coil parts according to the present invention can have a simple structure and processing capable of increasing magnetic permeability and accordingly improving an impedance characteristic of the coil parts, thereby implementing excellent performance and characteristic. | 06-13-2013 |
20130152379 | METHOD OF MANUFACTURING NOISE REMOVING FILTER - Disclosed herein is a method of manufacturing a noise removing filter, including preparing at least one conductive pattern, an insulating layer for covering the at least one conductive pattern, and a lower magnetic body including input/output stud terminals for electrically inputting and outputting electricity to and from the at least one conductive pattern; disposing a recognizable portion on upper surfaces of the input/output stud terminals; disposing an upper magnetic body on the recognizable portion and the insulating layer; polishing the upper magnetic body; and removing the recognizable portion such that a level of an upper surface of the upper magnetic body is higher than levels of the upper surfaces of the input/output stud terminals. | 06-20-2013 |
20130154770 | FILTER FOR REMOVING NOISE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a filter for removing noise, which includes: a lower magnetic body; an insulating layer disposed on the lower magnetic body and including at least one conductor pattern; input and output stud terminals electrically connected to the conductor pattern for electrical input and output of the conductor pattern; and an upper magnetic body consisting of an inner upper magnetic body including ferrite powder with a size corresponding to the interval between the input and output stud terminals and an outer upper magnetic body including ferrite powder with a size corresponding to the interval between the input and output stud terminals and an outer surface of the lower magnetic body. | 06-20-2013 |
20130162371 | FILTER FOR REMOVING NOISE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a filter for removing noise, which includes: a lower magnetic body; an insulating layer provided on the lower magnetic body and including at least one conductor pattern; and an upper magnetic body including a primary ferrite composite provided on the insulating layer and a secondary ferrite composite provided on the primary ferrite composite to cover a pore formed on a surface of the primary ferrite composite, and a method of manufacturing the same. | 06-27-2013 |
20130169381 | COMMON MODE FILTER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a common mode filter and a method of manufacturing the same. In order to implement a common mode filter with low shrinkage, high substrate sintered density, and high strength, the present invention provides a common mode filter including: a lower substrate; an insulating layer having a conductor pattern inside and provided on the lower substrate; an upper substrate provided on the insulating layer; and a ferrite core made of ferrite and provided in the center of the insulating layer, the lower substrate, and the upper substrate by penetrating the insulating layer, the lower substrate, and the upper substrate, and a method of manufacturing the same. | 07-04-2013 |
20130335871 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND COMPOSITE ELECTRONIC COMPONENT INCLUDING THE SAME - Disclosed herein are an electrostatic discharge protection device including: a substrate; a pair of electrodes formed on the substrate so as to be spaced apart from each other; and an insulating layer formed on the electrodes, wherein each of the electrodes has a shape in which it protrudes from a cross section thereof toward a surface thereof, and a manufacturing method thereof, and a composite electronic component including the same. | 12-19-2013 |
20140043129 | INDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF - Disclosed herein are an inductor element and a manufacturing method thereof. The inductor element includes: an electrode body formed of insulating material and having an internal electrode having a coil shape disposed therein; and external terminals formed on a part of the electrode body and each connected with both ends of the internal electrode, wherein electrode body is formed and separated on a base substrate, whereby a size of the inductor element is reduced. | 02-13-2014 |
20140062633 | COIL COMPONENT - Disclosed herein is a coil component including: an electrode structure made of an insulating material and including at least two internal electrodes vertically disposed therein in a height direction and having a coil shape; and external electrode terminals provided on an upper surface of the electrode structure, wherein a vertical distance (d3) between the internal electrodes is larger than a horizontal distance (d1) between the internal electrodes, in order to secure impedance capacity of a predetermined level and increase a cut-off frequency. | 03-06-2014 |