Sikkink
Jeffrey Sikkink, Longmont, CO US
Patent application number | Description | Published |
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20140247460 | CONFLICT RESOLUTION AND OPTIMIZATION FOR JOB DEFINITION FORMAT INSTRUCTIONS - Systems and methods are provided for addressing conflicts when merging Job Definition Format (JDF) instructions. The system includes a memory that stores rules for prioritizing Job Definition Format (JDF) instructions. The system also includes a controller able to receive a print job and to identify multiple sets of JDF instructions for the print job. The controller is further able to generate a merged set of JDF instructions from the JDF instructions in each of the identified sets, and to identify conflicts within the merged set between JDF instructions that share page ranges with each other. The controller is also able to resolve the conflicts by altering JDF instructions based on the rules stored in memory. | 09-04-2014 |
Jeffrey A. Sikkink, Longmont, CO US
Patent application number | Description | Published |
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20120188573 | Mechanism for Generating Index Separator Pages - A printing system is disclosed. The printing system includes a storage device and a print job manager that stores received print jobs in the storage device and facilitates the printing of multiple selected print jobs as a batch of print jobs. The print job manager includes a page generator to generate an index separator page including information for each of the selected print jobs with the batch of print jobs. | 07-26-2012 |
20120188594 | Print Job Management Mechanism - A printing system is disclosed. The printing system includes a storage device and a print job manager to store received print jobs in the storage device, select one or more of the stored print jobs upon detecting an occurrence of a condition that matches one or more pre-defined criteria and performing a processing action indicated by the pre-defined criteria. | 07-26-2012 |
Mark A. Sikkink, Layton, UT US
Patent application number | Description | Published |
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20140263480 | COUNTERSINK SEALANT APPLICATOR - An application tip and method for dispensing sealant into a countersunk hole, the tip having a hollow housing or body with an open end and a closed end; open end configured to be removably attached to and in fluid communication with a sealant source; closed end including a nozzle terminating in cylindrical member having a plurality of passages or fluid outlet openings. | 09-18-2014 |
Mark Ronald Sikkink, Chippewa Falls, WI US
Patent application number | Description | Published |
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20150278040 | High Speed Serial Link In-Band Lane Fail Over for RAS and Power Management - A system and method provide a communications link having a plurality of lanes, and an in-band, real-time physical layer protocol that keeps all lanes on-line, while failing lanes are removed, for continuous service during fail over operations. Lane status is monitored real-time at the physical layer receiver, where link error rate, per lane error performance, and other channel metrics are known. If a lane failure is established, a single round trip request/acknowledge protocol exchange with the remote port completes the fail over. If a failing lane meets an acceptable performance level, it remains on-line during the round trip exchange, resulting in uninterrupted link service. Lanes may be brought in or out of service to meet reliability, availability, and power consumption goals. | 10-01-2015 |
20150280746 | Low Latency Serial Data Encoding Scheme For Enhanced Burst Error Immunity and Long Term Reliability - A high performance computing system and method communicate data packets between computing nodes on a multi-lane communications link using a modified header bit encoding. Each data packet is provided with flow control information and error detection information, then divided into per-lane payloads. Sync header bits for each payload are added to the payloads in non-adjacent locations, thereby decreasing the probability that a single correlated burst error will invert both header bits. The encoded blocks that include the payload and the interspersed header bits are then simultaneously transmitted on the multiple lanes for reception, error detection, and reassembly by a receiving computing node. | 10-01-2015 |