Sidiropoulos
Aristidis Sidiropoulos, Huntington Beach, CA US
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20110316712 | ASSESSING STRUCTURAL REPAIR INTEGRITY - A strain measurement device to assess the integrity of a structural repair to a surface comprises a detector, a processor, and a memory module coupled to the processor. The memory module comprises logic instructions stored in a computer readable medium which, when executed by the processor, configure the processor to use the detector to obtain a first strain measurement from an external strain indicator, use the detector to obtain a second strain measurement from the measurement sensor after at least one stress test is applied to the structural repair, and generate a signal when a difference between the first strain measurement and the second strain measurement exceeds a threshold. | 12-29-2011 |
George Sidiropoulos, Patras GR
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20130169658 | MULTI-THREADED MULTI-FORMAT BLENDING DEVICE FOR COMPUTER GRAPHICS OPERATIONS - The disclosed invention provides a solution for the problem of blending colors in a graphics processing unit. The plurality of blending equations used in various graphics layers is performed with a programmable streaming processor. Multiple simultaneous threads are used to eliminate pipeline latency and memory stalls. Overlays of predefined blending modes are used to minimise the time instruction memory is updated. | 07-04-2013 |
20140192075 | Adaptive Lossy Framebuffer Compression with Controllable Error Rate - The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors. | 07-10-2014 |
20150067261 | Device and Method for Eliminating Complex Operations in Processing Systems based on Caching - The technology described in this application relates generally to computing processing systems and more specifically relates to systems that process data with resource intensive operations. Method and apparatus to lower the power consumption of the resource intensive operations are disclosed. Code analysis methods and run-time apparatus are presented that may eliminate the redundant operations (either complex calculations, memory fetches, or both). The techniques presented in this application are driven by special instructions inserted in the software code of the executing computer programs during the code generation process. Code analysis methods to insert the special instructions into the appropriate points in the source code of the target executing computer programs are presented. Run-time hardware mechanisms to support the potential elimination of redundant operations are also presented. Corresponding methods that might increase the number of eliminated operations by allowing limited errors to occur are also disclosed. | 03-05-2015 |
20150279090 | METHODS OF AND APPARATUS FOR ASSIGNING VERTEX AND FRAGMENT SHADING OPERATIONS TO A MULTI-THREADED MULTI-FORMAT BLENDING DEVICE - An exemplary aspect relates generally to graphics processing systems and more specifically relates to executing vertex and fragment shading operations to a pixel blender device. The technology is at least applicable to graphics processing systems in which vertex and fragment shading operations are executed by dedicated fragment and vertex units or by unified shading units. The graphics processing unit driver is responsible to determine if a shading operation can be assigned to a multi-threaded, multi-format pixel blender. Based on the determination, the fragment shading operations or the vertex shading operations or both are assigned to the pixel blender for execution; the execution of the fragment and/or vertex shading operations by the shader unit(s) is skipped. The determination is based on a code analysis. Forwarding shading operations from the fragment and vertex shaders, i.e., bypassing the shading units, to a programmable, multi-threaded and multi-format pixel blender may save electrical power consumption because a programmable, multi-threaded, and multi-format pixel blender is a less complex circuit compared to a fragment or a vertex or a unified shading unit. | 10-01-2015 |
20150347139 | DEVICE AND METHOD FOR APPROXIMATE MEMOIZATION - An exemplary embodiment relates generally to methods and apparatus of operating a computing device to perform approximate memoizations. Computer code analysis methods, special hardware units, and run-time apparatus that allow limited errors to occur are disclosed. A computer code generation process, part of compiler or interpreter of a computing system, targeting to insert special instructions in the software code of a computer program is also disclosed, wherein the special instructions may embed information to manage the approximation of value memoizations. The presented technology may reduce the electric power consumption of a computing system by reusing the results or part of the results of previous arithmetic or memory operations. Run-time hardware apparatus to manage the elimination of the operations and control the error introduced by approximate value memoizations are also disclosed. | 12-03-2015 |
Georgios Sidiropoulos, Partille SE
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20150256372 | RECEIVER ARRANGEMENT AND A METHOD THEREIN - An aspect of the solution herein is directed to a receiver arrangement ( | 09-10-2015 |
Nikolaos D. Sidiropoulos, Kambani GR
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20110243192 | METHOD AND APPARATUS FOR TRACKING A FREQUENCY-HOPPED SIGNAL - A frequency hopping signal receiving system comprising: a receiver for extracting discrete-time samples from the signal; a memory connected to the receiver for storing the extracted discrete-time samples from the signal; at least one processor operatively connected to the memory for: determining a state-space vector that captures relevant information to describe the dynamics of the signal; selecting a parameter to represent the probability of hopping associated with the signal; generating particle filters to estimate unknown parameters in the state-space vector based upon the extracted discrete-time samples by generating random particles that approximate the filtering distribution having importance weights; specifying the importance function in closed-form in a convenient mixture representation, which enables drawing particles and updating the importance weights; constructing an estimator to generate hop particles based upon observing at least one sample hop and then evaluating the estimator using a conditional expected value; using a spectrogram to generate particles in conjunction with an importance function; and estimating the hop frequency, hop time, and amplitude parameters, and a method thereof. | 10-06-2011 |
Nikolaos D. Sidiropoulos, Edina, MN US
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20160105230 | CHANNEL TRACKING AND TRANSMIT BEAMFORMING WITH FRUGAL FEEDBACK - In general, this disclosure describes techniques for beamforming using limited feedback that exploit the spatio-temporal channel correlation and avoid the limitations of codebook-based feedback and Markov chain modeling. In one example, a receiving device includes a plurality of receive antennas for receiving communication information, a memory for storing the communication information, and one or more processors for processing the communication information. The one or more processors are configured to receive, through a wireless communication channel, a pilot signal transmitted by a transmitting device, determine, based on the received pilot signal, channel state feedback comprising a quantized representation of the pilot signal as received at the receiving device, and send, through the wireless communication | 04-14-2016 |
Stefanos S. Sidiropoulos, Palo Alto, CA US
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20090138747 | Phase Adjustment Apparatus and Method for a Memory Device Signaling System - Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system. | 05-28-2009 |
20110248761 | Phase Adjustment Apparatus and Method for a Memory Device Signaling System - Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system. | 10-13-2011 |