Patent application number | Description | Published |
20110291187 | Double Diffused Drain Metal-Oxide-Semiconductor Devices with Floating Poly Thereon and Methods of Manufacturing The Same - A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion. | 12-01-2011 |
20120241900 | SELF DETECTION DEVICE FOR HIGH VOLTAGE ESD PROTECTION - An electrostatic discharge (ESD) protected device may include a substrate, an N-type well region disposed corresponding to a first portion of the substrate and having two N+ segments disposed at a surface thereof, an a P-type well region disposed proximate to a second portion of the substrate and having a P+ segment and an N+ segment. The two N+ segments may be spaced apart from each other and each may each be associated with an anode of the device. The N+ segment may be associated with a cathode of the device. A contact may be positioned in a space between the two N+ segments and connected to the P+ segment. The contact may form a parasitic capacitance that, in connection with a parasitic resistance formed in association with the N+ segment, provides self detection for high voltage ESD protection. | 09-27-2012 |
20120292689 | Semiconductor Structure and Method for Operating the Same - A semiconductor structure and a method for operating the same are provided. The semiconductor structure includes a substrate, a first doped region, a second doped region, a third doped region, a first trench structure and a second gate structure. The first doped region is in the substrate. The first doped region has a first conductivity type. The second doped region is in the first doped region. The second doped region has a second conductivity type opposite to the first conductivity type. The third doped region having the first conductivity type is in the second doped region. The first trench structure has a first gate structure. The first gate structure and the second gate structure are respectively on different sides of the second doped region. | 11-22-2012 |
20130049067 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 02-28-2013 |
20130056824 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion. | 03-07-2013 |
20130249007 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer. | 09-26-2013 |
20140106532 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME AND ESD CIRCUIT - A semiconductor structure and manufacturing method for the same, and an ESD circuit are provided. The semiconductor structure comprises a first doped region, a second doped region, a third doped region and a resistor. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity. The third doped region has the first type conductivity. The first doped region and the third doped region are separated by the second doped region. The resistor is coupled between the second doped region and the third doped region. An anode is coupled to the first doped region. A cathode is coupled to the third doped region. | 04-17-2014 |
20140197467 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE - A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure. | 07-17-2014 |
20140264581 | LOW ON RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided. | 09-18-2014 |