Patent application number | Description | Published |
20100264972 | FAST FLIP-FLOP STRUCTURE WITH REDUCED SET-UP TIME - A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch. | 10-21-2010 |
20110095811 | SUBSTRATE BIAS CONTROL CIRCUIT FOR SYSTEM ON CHIP - A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator. | 04-28-2011 |
20110248759 | RETENTION FLIP-FLOP - A master-slave retention flip-flop includes a master latch adapted to latch an input data signal and to output a latched master latch data signal based on an input clock signal, a slave latch coupled to an output of the master latch and adapted to output a latched slave latch data signal based on the input clock signal, and a retention latch embedded within one of the master and slave latches adapted to preserve data in a power down mode based on a power down control signal. | 10-13-2011 |
20120112352 | INTEGRATED CIRCUIT SYSTEM WITH DISTRIBUTED POWER SUPPLY - An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The integrated circuit having circuit blocks, that operate at different operating voltages and voltage regulator modules die bonded to the second bond pads of the integrated circuit. The voltage regulator modules converting a power supply voltage to the operating voltage of a respective circuit block and supply the respective operating voltage to the circuit block via the second bond pads. | 05-10-2012 |
20120124248 | PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT - An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit. | 05-17-2012 |
20120319717 | METHOD AND APPARATUS FOR 3D IC TEST - An apparatus comprises a die comprising a plurality of switch/router circuits; and a plurality of additional dies. Each respective one of the plurality of additional dies comprises: a respective network interface, which is electrically coupled to a respective one of the plurality of switch/router circuits; and a respective interconnection test logic, which is electrically coupled to the respective network interface and the interconnection test logic in at least one other one of the plurality of additional dies. | 12-20-2012 |
20130106463 | THREE DIMENSIONAL INTEGRATED CIRCUIT CONNECTION STRUCTURE AND METHOD | 05-02-2013 |
20130120021 | 3D IC STRUCTURE AND METHOD - An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus. | 05-16-2013 |
20130135018 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits. | 05-30-2013 |
20140015576 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER - An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop. | 01-16-2014 |
20140015599 | SUBSTRATE BIAS CONTROL CIRCUIT - An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value. | 01-16-2014 |
20140021989 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter. | 01-23-2014 |
20140091834 | 3D IC STRUCTURE AND METHOD - An apparatus comprises a first integrated circuit (IC) die, and a second IC die stacked on the first IC die. The first and second IC dies are operational independently of each other. Each respective one of the first and second IC dies has: at least one circuit for performing a function; an operation block coupled to selectively disconnect the circuit from power; and an output enable block coupled to selectively connect the circuit to at least one data bus. | 04-03-2014 |
20140145757 | THREE DIMENSIONAL INTEGRATED CIRCUIT CONNECTION STRUCTURE AND METHOD - An integrated circuit die stack comprises a first die and a second die connected to each other. Each of the first and second dies comprise a functional circuitry, a plurality of first contacts on a first surface of the respective die, a plurality of second contacts on a second surface of the respective die, and a programmable array coupled to the functional circuitry and the plurality of first and second contacts. The programmable array includes a plurality of programmable connection elements in the first and second dies. The programmable connection elements are programmed to bypass one of the first and second dies. | 05-29-2014 |
20140207992 | PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT - An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit. | 07-24-2014 |
20140210077 | INTEGRATED CIRCUIT SYSTEM WITH DISTRIBUTED POWER SUPPLY - An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit comprises first bond pads, and is electrically connected to the interposer at a first position of the interposer via the first bond pads. The first integrated circuit also comprises second bond pads. The first integrated circuit further comprises at least two circuit blocks. The at least two circuit blocks are configured to operate at different operating voltages. The at least one voltage regulator module is electrically connected to the first integrated circuit via the second bond pads, and the at least one voltage regulator module is configured to convert a received power supply voltage to the respective operating voltage of one of the at least two circuit blocks and supply the respective operating voltage via the second bond pads. | 07-31-2014 |
20140333355 | PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER - A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL. | 11-13-2014 |
20140375408 | INDUCTOR ASSEMBLY AND METHOD OF USING SAME - An inductor assembly generally comprises at least one helical inductive component comprising that includes a plurality of conductive line layers having conductive lines therein. A plurality of vias are configured to couple conductive lines from two or more conductive line layers such that a spacing between two adjacent parallel conductive lines, in different conductive line layers from each other, is two or more times a distance between respective bottom surfaces of two adjacent conductive line layers. | 12-25-2014 |
20150077160 | INTEGRATED CIRCUIT DIE STACK - An integrated circuit die stack comprises a first die coupled with a second die. The first die has a first memory volume. The second die has a second memory volume different from the first memory volume. Each of the first and second dies comprises a functional circuitry and a programmable array coupled with the functional circuitry. The programmable arrays in the first and second dies are programmed to bypass one of the first die or the second die having the smaller of the first memory volume or the second memory volume at a first time period. | 03-19-2015 |