Patent application number | Description | Published |
20100057000 | MALECOT WITH TEXTILE COVER - A malecot device includes a textile material covering its deployable malecot wing portion. The textile material is woven in a manner allowing it to be compactly disposed around an undeployed malecot and then expanded to cover malecot wings when those wings are deployed to an expanded outer device diameter. | 03-04-2010 |
20100063576 | Prosthesis with Moveable Fenestration - An endoluminal prosthesis with a moveable fenestration including a tubular graft body having a proximal end, a distal end, a surface plane at least one fenestration having a perimeter disposed in a sidewall of the tubular body between the proximal end and the distal end, a first biocompatible graft material, and a second biocompatible graft material adjacent to and surrounding the perimeter of the at least one fenestration. The second biocompatible graft material has at least one characteristic different from the first biocompatible graft material and is more flexible than the first biocompatible graft material and is movable relative to the surface plane of the tubular graft body. | 03-11-2010 |
20100161025 | VARIABLE WEAVE GRAFT WITH METAL STRAND REINFORCEMENT FOR IN SITU FENESTRATION - The disclosure relates to an implantable woven graft for bridging a defect in a main vessel near one or more branch vessels. The graft includes a region of reduced density. Reduced density regions are alignable with at least one of the one or more branch vessels, and are suitable for in situ fenestration, for example by perforation. The disclosed examples are particularly suited for bridging abdominal aortic aneurysms. | 06-24-2010 |
20110046654 | TEXTILE-REINFORCED HIGH-PRESSURE BALLOON - A textile-reinforced medical dilation balloon is provided, including a woven tubular textile sleeve with substantially longitudinal thermoplastic warp threads and at least one weft thread woven substantially perpendicular relative to the warp threads, where the sleeve defines a sleeve lumen. A medical dilation balloon is disposed within the sleeve lumen, and an adhesive coating substantially covers the inner and outer surfaces of the sleeve, attaching it to the balloon. | 02-24-2011 |
20110251588 | Infusion Mechanism And Method - An infusion mechanism for treating an intraluminal site in a patient includes an infusion catheter having an elongate body with a proximal body end defining at least one fluid supply orifice, and a distal body end. The elongate body defines a high head loss lumen in fluid communication with a first set of side ports defining a proximal infusion zone. The elongate body further defines a low head loss lumen in fluid communication with a second set of side ports defining a distal infusion zone. | 10-13-2011 |
20120035586 | Infusion Catheter And Method - An infusion catheter includes an elongate catheter body having a proximal body component and a distal body component. The distal body component includes a distal body outer surface and a distal body inner surface defining an infusion lumen. The distal body component further includes a skeleton, and a porous infusion control textile contacting the skeleton and extending circumferentially about a longitudinal axis of the catheter and defining a fluid emission profile thereof. The porous infusion control textile further includes a fiber network having a higher density space filling configuration at a proximal textile end and a lower density space filling configuration at a distal textile end, and defining a pressure sensitive flow rate property and a pressure insensitive flow distribution property of the fluid emission profile. | 02-09-2012 |
20120168022 | WOVEN FABRIC HAVING COMPOSITE YARNS FOR ENDOLUMINAL DEVICES - A woven fabric for a low profile implantable medical device includes a plurality of textile strands of a composite yarn aligned in a first direction interlaced with a plurality of textile strands of the composite yarn aligned in a second direction. The composite yarn includes a combination of a first material and a second material. The textile strands have a size between about 10 denier to about 20 denier. The first material has at least one characteristic different from the second material and the second material reacts favorably with blood when placed within an artery. | 07-05-2012 |
20120171917 | COMPOSITE WOVEN FABRIC FOR ENDOLUMINAL DEVICES - A composite woven fabric for a low profile implantable medical device having a plurality of textile strands of a first material aligned in a first direction interlaced with a plurality of textile strands of a second material. The textile strands have a size between about 10 denier to about 20 denier. The first material has at least one characteristic different from the second material and the second material reacts more favorably with blood when placed within an artery. | 07-05-2012 |
20130018410 | THROMBUS REMOVAL DEVICE - A thrombus removal device includes a shaft with a distal end and a proximal end, a sheath with a distal end and a proximal end, and a helical coil attached at a proximal end to the distal end of the shaft and is disposed within the lumen of the sheath in a closed configuration. The helical coil includes a plurality of body portions with turns spaced apart longitudinally and laterally to facilitate screwing the helical coil into a thrombus and also providing an open area into which the thrombus can be captured. A distal tip of the helical coil is provided with a loop, an angle of which is about the same as the angle of at least one body portion. The helical coil assumes an open configuration when the sheath is retracted proximally from the distal tip. | 01-17-2013 |
20130046282 | Method Of Treating An Intravascular Site In A Patient, And Thrombolysis Catheter Therefor - A method of treating an intravascular site in a patient includes spraying jets of treatment fluid out of spray orifices formed in an elongate catheter body, and changing an impingement pattern of the treatment fluid on material within the intravascular site in response to a torque induced by a back pressure of the jets. A thrombolysis catheter includes an elongate catheter body having a plurality of spray orifices formed in a body wall, and communicating with a fluid lumen longitudinally extending in the elongate catheter body. The plurality of spray orifices define a torque inducing spray jet pattern, whereby a back pressure of spray jets exiting the spray orifices induces a torque on the elongate catheter body. | 02-21-2013 |
20130046330 | MULTI-LAYER FILTRATION DEVICE - A filter device assembly and a method of using such a device to capture and remove embolic material from a body lumen or blood vessel is provided. The filter device assembly generally comprises a structure having a collapsed state and an expanded state with first, second, and optionally N additional filter members circumferentially attached thereto. Each filter member forms an annulus chamber with the first filter member having porosity P | 02-21-2013 |
20140081315 | Multi-Layer Filtration Device - A filter device assembly and a method of using such a device to capture and remove embolic material from a body lumen or blood vessel is provided. The filter device assembly generally comprises a structure having a collapsed state and an expanded state with first, second, and optionally N additional filter members circumferentially attached thereto. Each filter member forms an annulus chamber with the first filter member having porosity P | 03-20-2014 |
Patent application number | Description | Published |
20090193376 | CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures. | 07-30-2009 |
20090271752 | Legalization of VLSI circuit placement with blockages using hierarchical row slicing - A hierarchical method of legalizing the placement of logic cells in the presence of blockages selectively classifies the blockages into at least two different sets based on size (large and small). Movable logic cells are relocated first among coarse regions between large blockages to remove overlaps among the cells and the large blockages without regard to small blockages (while satisfying capacity constraints of the coarse regions), and thereafter the movable logic cells are relocated among fine regions between small blockages to remove all cell overlaps (while satisfying capacity constraints of the fine regions). The coarse and fine regions may be horizontal slices of the placement region having a height corresponding to a single circuit row height of the design. Cells are relocated with minimal perturbation from the previous placement, preserving wirelength and timing optimizations. The legalization technique may utilize more than two levels of granularity with multiple relocation stages. | 10-29-2009 |
20100192155 | SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 07-29-2010 |
20110072407 | Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design - An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits. | 03-24-2011 |
20120036491 | Constraint Programming Based Method for Bus-Aware Macro-Block Pin Placement in a Hierarchical Integrated Circuit Layout - Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations. | 02-09-2012 |
20120284733 | Scheduling for Parallel Processing of Regionally-Constrained Placement Problem - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 11-08-2012 |
20120297355 | WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN - A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved. | 11-22-2012 |
20140007036 | SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN | 01-02-2014 |
20140033154 | Scheduling for Parallel Processing of Regionally-Constrained Placement Problem - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 01-30-2014 |
20140149957 | STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS - A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design. | 05-29-2014 |
20140359546 | STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SYNTHESIS OF AN INTEGRATED CIRCUIT - Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets. | 12-04-2014 |
20150113496 | THERMALLY AWARE PIN ASSIGNMENT AND DEVICE PLACEMENT - Embodiments of the disclosure relate to methods for facilitating the design of an integrated circuit (IC) using thermally aware pin assignment and device placement. The method includes creating a layout for the IC, the layout including a plurality of macros each having devices and pin assignments and revising the layout for the IC by repositioning a macro or a device to meet a timing requirement of the IC. The method also includes creating a thermal map of the IC based on the layout for the IC and a workload model for the IC and identifying at least one thermally critical pin assignment based on the thermal map of the IC. The method includes revising the layout by repositioning a thermally critical pin assignment and a device. | 04-23-2015 |
Patent application number | Description | Published |
20090080533 | VIDEO DECODING USING CREATED REFERENCE PICTURES - Reference pictures can be created to assist with video decoding. For example, a method for decoding video can comprise receiving an encoded video bit stream, determining that a reference picture is needed, and creating and inserting the reference picture into the encoded video bit stream. A method for decoding video can also comprise receiving an encoded video bit stream, performing bit stream parsing, determining that a reference picture is needed, selecting a representation level for the reference picture, and conveying data for the selected reference picture to a hardware accelerated graphics processing unit. Various video operations, such as creating reference pictures and related information, can be performed by central processing units, while other video decoding operations can be performed by graphics processing units. | 03-26-2009 |
20100128778 | ADJUSTING HARDWARE ACCELERATION FOR VIDEO PLAYBACK BASED ON ERROR DETECTION - Adjustment of hardware acceleration level in a video decoder utilizing hardware acceleration is described. Errors are detected in a bitstream as it is decoded using different levels of error detection based on decoding characteristics. A statistical analysis is performed on the error values as they are detected. In one technique, if the bitstream is categorized as fitting a high error rate state in a bitstream model, then hardware acceleration is dropped. In another technique, error statistics based on run-lengths of good and bad bitstream units are kept, and compared to predetermined thresholds. If the thresholds are exceeded, the hardware acceleration level is dropped. The level is dropped in order to take advantage of superior error handing abilities of software-based decoding over hardware-accelerated decoding. | 05-27-2010 |
20110013889 | IMPLEMENTING CHANNEL START AND FILE SEEK FOR DECODER - A video bit stream with pictures comprising inter-coded content can be decoded upon receiving a channel start or file seek instruction. Pictures for beginning decoding and display of the bit stream can be selected based at least in part on one or more tuning parameters that set a preference between a latency of beginning to display video and possible defects in the displayed video. In some embodiments, to implement decoding upon a channel start or file seek, one or more types of data are generated for one or more pictures. For example, picture order counts are generated for pictures after a channel start or file seek operation. As another example, a decoder generates a frame number value that triggers re-initialization of a reference picture buffer before decoding after a channel start or file seek operation. | 01-20-2011 |
20110018889 | MEDIA PROCESSING COMPARISON SYSTEM AND TECHNIQUES - A media processing comparison system (“MPCS”) and techniques facilitate concurrent, subjective quality comparisons between media presentations produced by different instances of media processing components performing the same functions (for example, instances of media processing components in the form of hardware, software, and/or firmware, such as parsers, codecs, decryptors, and/or demultiplexers, supplied by the same or different entities) in a particular media content player. The MPCS receives an ordered stream of encoded media samples from a media source, and decodes a particular encoded media sample using two or more different instances of media processing components. A single renderer renders and/or coordinates the synchronous presentation of decoded media samples from each instance of media processing component(s) as separate media presentations. The media presentations may be subjectively compared and/or selected for storage by a user in a sample-by-sample manner. | 01-27-2011 |
20110193978 | GENERIC PLATFORM VIDEO IMAGE STABILIZATION - Video image stabilization provides better performance on a generic platform for computing devices by evaluating available multimedia digital signal processing components, and selecting the available components to utilize according to a hierarchy structure for video stabilization performance for processing parts of the video stabilization. The video stabilization has improved motion vector estimation that employs refinement motion vector searching according to a pyramid block structure relationship starting from a downsampled resolution version of the video frames. The video stabilization also improves global motion transform estimation by performing a random sample consensus approach for processing the local motion vectors, and selection criteria for motion vector reliability. The video stabilization achieves the removal of hand shakiness smoothly by real-time one-pass or off-line two-pass temporal smoothing with error detection and correction. | 08-11-2011 |
20120147973 | LOW-LATENCY VIDEO DECODING - Techniques and tools for reducing latency in video decoding for real-time communication applications that emphasize low delay. For example, a tool such as a video decoder selects a low-latency decoding mode. Based on the selected decoding mode, the tool adjusts output timing determination, picture boundary detection, number of pictures in flight and/or jitter buffer utilization. For low-latency decoding, the tool can use a frame count syntax element to set initial output delay for a decoded picture buffer, and the tool can use auxiliary delimiter syntax elements to detect picture boundaries. To further reduce delay in low-latency decoding, the tool can reduce number of pictures in flight for multi-threaded decoding and reduce or remove jitter buffers. The tool receives encoded data, performs decoding according to the selected decoding mode to reconstruct pictures, and outputs the pictures for display. | 06-14-2012 |
20120163470 | IMAGE AND VIDEO DECODING IMPLEMENTATIONS - Efficient operations in image or video decoding. For example, a tool such as an image or video decoder receives and decodes encoded data for a picture in a bitstream. As part of the decoding, the tool adapts a multi-symbol lookup table to use in decoding of symbols then decodes the symbols using the multi-symbol lookup table, producing exactly correct results. The tool can also perform selectively truncated inverse frequency transforms. For a given block, the tool identifies upper horizontal and vertical frequencies among non-zero coefficients for the block and, based on the upper frequency values, selectively applies a simplified inverse frequency transform to transform coefficients for the block without hurting decoding quality. Using restart markers in the bitstream, the tool can organize multiple blocks of the picture as partitions. The tool decodes at least some of the partitions in parallel on a partition-by-partition basis using multiple processing cores. | 06-28-2012 |
20120250772 | MULTI-THREADED IMPLEMENTATIONS OF DEBLOCK FILTERING - Multi-threaded implementations of deblock filtering improve encoding and/or decoding efficiency. For example, a video encoder or decoder partitions a video picture into multiple segments. The encoder/decoder selects between multiple different patterns for splitting operations of deblock filtering into multiple passes. The encoder/decoder organizes the deblock filtering as multiple tasks, where a given task includes the operations of one of the passes for one of the segments. The encoder/decoder then performs the tasks with multiple threads. The performance of the tasks is constrained by task dependencies which, in general, are based at least in part on which lines of the picture are in the respective segments and which deblock filtering operations are in the respective passes. The task dependencies can include a cross-pass, cross-segment dependency between a given pass of a given segment and an adjacent pass of an adjacent segment. | 10-04-2012 |
20120320967 | ADAPTIVE CODEC SELECTION - Disclosed herein are tools and techniques for storing and using video processing tool configuration information that can identify combinations of video processing tools to be used for processing video. In one exemplary embodiment, video processing tools of a computing system are identified. The performance of a combination of the video processing tools is measured. The performance measurement is compared with another performance measurement of another combination of the video processing tools. Based on the comparison, video processing tool configuration information is set. In another exemplary embodiment, video processing tool configuration information indicating a combination of video processing tools is accessed, and video data is processed using the combination of video processing tools based on the video processing tool configuration information. | 12-20-2012 |
20130033612 | REDUCED LATENCY VIDEO STABILIZATION - Reduced latency video stabilization methods and tools generate truncated filters for use in the temporal smoothing of global motion transforms representing jittery motion in captured video. The truncated filters comprise future and past tap counts that can be different from each other and are typically less than those of a baseline filter providing a baseline of video stabilization quality. The truncated filter future tap count can be determined experimentally by comparing a smoothed global motion transform set generated by applying a baseline filter to a video segment to those generated by multiple test filter with varying future tap counts, then settings the truncated filter future tap count based on an inflection point on an error-future tap count curve. A similar approach can be used to determine the truncated filter past tap count. | 02-07-2013 |
20130051478 | MEMORY MANAGEMENT FOR VIDEO DECODING - Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip. The decoder also determines second memory usage settings known to be sufficient for decoding of the clip. During decoding, memory usage is initially set according to the first settings. Memory usage is adaptively increased during decoding, subject to theoretical limits in the second settings. With adaptive early release of side information, the decoder can release side information memory for a picture earlier than the decoder releases image plane memory for the picture. The decoder can also adapt memory usage for decoded transform coefficients depending on whether the coefficients are for intra-coded blocks or inter-coded blocks, and also exploit the relative sparseness of non-zero coefficient values. | 02-28-2013 |
20130108248 | IMPLEMENTING CHANNEL START AND FILE SEEK FOR DECODER | 05-02-2013 |
20130141642 | ADAPTIVE CONTROL OF DISPLAY REFRESH RATE BASED ON VIDEO FRAME RATE AND POWER EFFICIENCY - A battery operated device, having a display with two or more available refresh rates, has its refresh rate selected so as to match the video frame rate of video data played back on the display. This selection is made by coordinating the resources in the device that are used to process the video from its reception through to its display. | 06-06-2013 |
20130151972 | MEDIA PROCESSING COMPARISON SYSTEM AND TECHNIQUES - A media processing comparison system (“MPCS”) and techniques facilitate concurrent, subjective quality comparisons between media presentations produced by different instances of media processing components performing the same functions (for example, instances of media processing components in the form of hardware, software, and/or firmware, such as parsers, codecs, decryptors, and/or demultiplexers, supplied by the same or different entities) in a particular media content player. The MPCS receives an ordered stream of encoded media samples from a media source, and decodes a particular encoded media sample using two or more different instances of media processing components. A single renderer renders and/or coordinates the synchronous presentation of decoded media samples from each instance of media processing component(s) as separate media presentations. The media presentations may be subjectively compared and/or selected for storage by a user in a sample-by-sample manner. | 06-13-2013 |
20130215978 | METADATA ASSISTED VIDEO DECODING - A video decoder is disclosed that uses metadata in order to make optimization decisions. In one embodiment, metadata is used to choose which of multiple available decoder engines should receive a video sequence. In another embodiment, the optimization decisions can be based on length and location metadata information associated with a video sequence. Using such metadata information, a decoder engine can skip start-code scanning to make the decoding process more efficient. Also based on the choice of decoder engine, it can decide whether emulation prevention byte removal shall happen together with start code scanning or not. | 08-22-2013 |
20140092998 | FRAME PACKING AND UNPACKING HIGHER-RESOLUTION CHROMA SAMPLING FORMATS - Video frames of a higher-resolution chroma sampling format such as YUV 4:4:4 are packed into video frames of a lower-resolution chroma sampling format such as YUV 4:2:0 for purposes of video encoding. For example, sample values for a frame in YUV 4:4:4 format are packed into two frames in YUV 4:2:0 format. After decoding, the video frames of the lower-resolution chroma sampling format can be unpacked to reconstruct the video frames of the higher-resolution chroma sampling format. In this way, available encoders and decoders operating at the lower-resolution chroma sampling format can be used, while still retaining higher resolution chroma information. In example implementations, frames in YUV 4:4:4 format are packed into frames in YUV 4:2:0 format such that geometric correspondence is maintained between Y, U and V components for the frames in YUV 4:2:0 format. | 04-03-2014 |
20140294094 | CUSTOM DATA INDICATING NOMINAL RANGE OF SAMPLES OF MEDIA CONTENT - A media processing tool adds custom data to an elementary media bitstream or media container. The custom data indicates nominal range of samples of media content, but the meaning of the custom data is not defined in the codec format or media container format. For example, the custom data indicates the nominal range is full range or limited range. For playback, a media processing tool parses the custom data and determines an indication of media content type. A rendering engine performs color conversion operations whose logic changes based at least in part on the media content type. In this way, a codec format or media container format can in effect be extended to support full nominal range media content as well as limited nominal range media content, and hence preserve full or correct color fidelity, while maintaining backward compatibility and conformance with the codec format or media container format. | 10-02-2014 |
20140314233 | PROTECTED MEDIA DECODING USING A SECURE OPERATING SYSTEM - Disclosed herein are representative embodiments of tools and techniques for facilitating decoding of protected media information using a secure operating system. According to one exemplary technique, encoded media information that is encrypted is received at a secure process of a secure operating system of a computing system. At least a portion of the encoded media information that is encrypted is decrypted in the secure process. The portion of the encoded media information includes header information. Additionally, the header information is sent from the secure operating system to a software decoder for control of decoding hardware. The software decoder is included in a process for an application. Also, the decoding hardware is securely provided access to the encoded media information for decoding of the encoded media information to produce decoded media information. | 10-23-2014 |
20150036010 | GENERIC PLATFORM VIDEO IMAGE STABILIZATION - Video image stabilization provides better performance on a generic platform for computing devices by evaluating available multimedia digital signal processing components, and selecting the available components to utilize according to a hierarchy structure for video stabilization performance for processing parts of the video stabilization. The video stabilization has improved motion vector estimation that employs refinement motion vector searching according to a pyramid block structure relationship starting from a downsampled resolution version of the video frames. The video stabilization also improves global motion transform estimation by performing a random sample consensus approach for processing the local motion vectors, and selection criteria for motion vector reliability. The video stabilization achieves the removal of hand shakiness smoothly by real-time one-pass or off-line two-pass temporal smoothing with error detection and correction. | 02-05-2015 |
20150062353 | AUDIO VIDEO PLAYBACK SYNCHRONIZATION FOR ENCODED MEDIA - Techniques are described for inserting encoded markers into encoded audio-video content. For example, encoded audio-video content can be received and corresponding encoded audio and video markers can be inserted. The encoded audio and video markers can be inserted without changing the overall duration of the encoded audio and video streams and without changing most or all of the properties of the encoded audio and video streams. Corresponding encoded audio and video markers can be inserted at multiple locations (e.g., sync locations) in the encoded audio and video streams. Audio-video synchronization testing can be performed using encoded audio-video content with inserted encoded audio-video markers. | 03-05-2015 |
20150237356 | HOST ENCODER FOR HARDWARE-ACCELERATED VIDEO ENCODING - By controlling decisions for high layers of bitstream syntax for encoded video, a host encoder provides consistent behaviors even when used with accelerator hardware from different vendors across different hardware platforms. For example, the host encoder controls high-level behaviors of encoding and sets values of syntax elements for sequence layer and picture layer of an output bitstream (and possibly other layers such as slice-header layer), while using only a small amount of computational resources. An accelerator that includes the accelerator hardware then controls encoding decisions for lower layers of syntax, in a manner consistent with the values of syntax elements set by the host encoder, setting values of syntax elements for the lower layers of syntax, which allows the accelerator some flexibility in making its encoding decisions. | 08-20-2015 |
20150237381 | MULTI-THREADED IMPLEMENTATIONS OF DEBLOCK FILTERING - Multi-threaded implementations of deblock filtering improve encoding and/or decoding efficiency. For example, a video encoder or decoder partitions a video picture into multiple segments. The encoder/decoder selects between multiple different patterns for splitting operations of deblock filtering into multiple passes. The encoder/decoder organizes the deblock filtering as multiple tasks, where a given task includes the operations of one of the passes for one of the segments. The encoder/decoder then performs the tasks with multiple threads. The performance of the tasks is constrained by task dependencies which, in general, are based at least in part on which lines of the picture are in the respective segments and which deblock filtering operations are in the respective passes. The task dependencies can include a cross-pass, cross-segment dependency between a given pass of a given segment and an adjacent pass of an adjacent segment. | 08-20-2015 |
Patent application number | Description | Published |
20100220868 | COUPLING OF SPEAKERS WITH INTEGRATED CIRCUIT - Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces. | 09-02-2010 |
20100220875 | POP-UP NOISE SUPPRESSION IN AUDIO - Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit. | 09-02-2010 |
20120080945 | Power Management Unit Systems and Methods - Systems and methods provide for a power management unit and its operation. The power management unit includes: a step-down power converter configured to receive a first voltage and output a second voltage, wherein the second voltage is less than the first voltage and at least one step-up power converter configured to receive the second voltage and output a third voltage, wherein the third voltage is greater than the second voltage. It also includes an inductive element connected to the step-down power converter and the at least one step-up power converter and configured to store energy and selectively release the stored energy, wherein the inductive element is time shared by both the step-down power converter and the at least one step-up power converter; and a finite state machine configured to control the time sharing of the inductive element. | 04-05-2012 |
20120249202 | Pulse Width Modulation for Switching Amplifier - A device and a method for implementing pulse width modulation for switching amplifiers ( | 10-04-2012 |
20120306502 | Circuit for Controlling Current to Light-Emitting Diode (LED) - The present invention discloses a current controlling circuit wherein the circuit ( | 12-06-2012 |
20140139046 | Method and Electrical Interface Circuit Enabling Multiplexing - An electrical interface circuit is disclosed. The circuit comprises a microphone circuit ( | 05-22-2014 |
20140334632 | POP-UP NOISE SUPPRESSION IN AUDIO - Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit. | 11-13-2014 |
20150045095 | POWER AMPLIFIER PROVIDING HIGH EFFICIENCY - A power amplifier containing a DC-DC converter, a linear amplifier and a control block. The DC-DC converter receives power from a power source and generates a regulated power supply voltage whose magnitude is controlled by the magnitude of a control signal provided to the DC-DC converter. The linear amplifier receives an input signal and generates a power-amplified output signal, and receives the regulated power supply voltage for operation. The control block is coupled to receive the input signal, and generates the control signal with a magnitude based on the amplitude of the input signal. The regulated power supply voltage is modulated based on the amplitude of the input signal, for peak-to-peak amplitudes of the power-amplified output greater than or less than or equal to the magnitude of the power source. High efficiency for the power amplifier is thereby obtained. | 02-12-2015 |
20150070090 | SUSPEND MODE IN CHARGE PUMP - A device may be associated with a power source. The device may include a charge pump configured to output a pulse-width modulated voltage based upon an input voltage from the power source, with the pulse-width modulated voltage varying between a first voltage and a second voltage. The device may also include a low-pass filter comprising an output capacitor, with the output capacitor being configured to average the pulsed-width modulated voltage and to output a filtered voltage having a value different than that of the input voltage. The device may further include a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass filter is below a threshold load. | 03-12-2015 |
Patent application number | Description | Published |
20090042404 | Semiconductor processing - Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process. | 02-12-2009 |
20090176379 | Semiconductor Processing Methods, And Methods For Forming Silicon Dioxide - Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The semiconductor substrate may be heated by radiating thermal energy from the outer region to the inner region. The heating may eventually achieve thermal equilibrium. However, before thermal equilibrium of the outer and inner regions is reached, and while the outer region is warmer than the inner region, at least two reactants are sequentially introduced into the reaction chamber. The reactants may together form a single composition on the deposition surface through a quasi-ALD process. | 07-09-2009 |
20090191499 | METHODS AND APPARATUSES FOR HEATING SEMICONDUCTOR WAFERS - Methods and apparatuses for heat treatment of semiconductor wafers are disclosed herein. A method of heating a semiconductor wafer in accordance with one embodiment includes heating the wafer in a loading enclosure of a heat treatment system above an ambient temperature external to the loading enclosure. The method also includes moving the heated wafer from the loading enclosure into a processing enclosure of the heat treatment system. In particular embodiments, the method can further include heating a flow of purge gas above the ambient temperature and introducing the flow of heated purge gas into the loading enclosure while the wafer is in the loading enclosure. In still further embodiments, the method can include heating a flow of process gas to a processing temperature and introducing the heated flow of process gas into the processing enclosure while the wafer is in the processing enclosure. | 07-30-2009 |
20090275214 | METHODS OF REDUCING DEFECT FORMATION ON SILICON DIOXIDE FORMED BY ATOMIC LAYER DEPOSITION (ALD) PROCESSES AND METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES - Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate. | 11-05-2009 |
20100112191 | SYSTEMS AND ASSOCIATED METHODS FOR DEPOSITING MATERIALS - Several embodiments of systems for depositing materials and associated methods of operation are disclosed herein. In one embodiment, the system includes a reaction chamber having an inlet and an outlet, a gas source coupled to the inlet of the reaction chamber, and a neutralizer source coupled to the outlet of the reaction chamber. The gas source contains a first precursor gas, a second precursor gas, and a purge gas. The neutralizer source contains a neutralizing agent configured to reduce a rate of reaction between the first precursor gas and the second precursor gas. | 05-06-2010 |
20110008972 | METHODS FOR FORMING AN ALD SIO2 FILM - Methods of forming a silicon dioxide material by an atomic layer deposition process and methods of preparing a substrate for the formation of a silicon dioxide material by an atomic layer deposition process are provided. In at least one such method, prior to forming the silicon oxide material, at least one pump and exhaust cycle is conducted. Such a pump and exhaust cycle includes at least one pump step, whereby a purge gas is pumped into the reaction chamber, and at least one exhaust step, whereby the purge gas is exhausted from a reaction chamber. The silicon oxide material is then formed on a surface of the substrate. | 01-13-2011 |
20110081786 | METHODS OF REDUCING DEFECT FORMATION ON SILICON DIOXIDE FORMED BY ATOMIC LAYER DEPOSITION (ALD) PROCESSES - Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished by performing processing on the silicon dioxide subsequent to deposition by ALD. The post-deposition processing may include at least one of a pump/purge cycle and a water exposure cycle performed after formation of the silicon dioxide on a substrate. | 04-07-2011 |
20110185970 | SEMICONDUCTOR PROCESSING - Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process. | 08-04-2011 |
20110263135 | Semiconductor Processing Methods, And Methods For Forming Silicon Dioxide - Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The semiconductor substrate may be heated by radiating thermal energy from the outer region to the inner region. The heating may eventually achieve thermal equilibrium. However, before thermal equilibrium of the outer and inner regions is reached, and while the outer region is warmer than the inner region, at least two reactants are sequentially introduced into the reaction chamber. The reactants may together form a single composition on the deposition surface through a quasi-ALD process. | 10-27-2011 |
20120214285 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 08-23-2012 |
20120256259 | SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF - The present invention provides a single-sided access device including an active fin structure comprising a source region and a drain region; an insulating layer interposed between the source region and the drain region; a trench isolation structure disposed at one side of the active fin structure; a single-sided sidewall gate electrode disposed on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by trench isolation structure and the single-sided sidewall gate electrode; and a gate protrusion laterally and electrically extended from the single-sided sidewall gate electrode and embedded between the source region and the drain region under the insulating layer. | 10-11-2012 |
20120299088 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 11-29-2012 |
20120329274 | METHOD OF FABRICATING A CELL CONTACT AND A DIGIT LINE FOR A SEMICONDUCTOR DEVICE - The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line. | 12-27-2012 |
20130049074 | METHODS FOR FORMING CONNECTIONS TO A MEMORY ARRAY AND PERIPHERY - Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming a step between the periphery stack and the array stack. The step is removed during subsequent processing, and connections are formed from the conductive materials remaining on the array and the periphery. In some embodiments, the step is removed before any photolithographic processes. | 02-28-2013 |
20130187220 | VERTICAL MEMORY DEVICES, APPARATUSES INCLUDING VERTICAL MEMORY DEVICES, AND METHODS FOR FORMING SUCH VERTICAL MEMORY DEVICES AND APPARATUSES - Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods. | 07-25-2013 |
20130187279 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING BURIED DIGIT LINES AND RELATED METHODS - Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts are formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region. | 07-25-2013 |
20130237023 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 09-12-2013 |
20140017865 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-16-2014 |
20140054718 | Arrays of Vertically-Oriented Transistors, And Memory Arrays Including Vertically-Oriented Transistors - An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed. | 02-27-2014 |
20140057402 | Methods of Forming Memory Arrays and Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material. | 02-27-2014 |
20140070306 | VERTICAL MEMORY DEVICES AND APPARATUSES - Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods. | 03-13-2014 |
20140073100 | Methods Of Forming A Vertical Transistor, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 03-13-2014 |
20140252532 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 09-11-2014 |
20140264754 | METHODS OF FORMING DOPED ELEMENTS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES - Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures. | 09-18-2014 |
20140315364 | Methods Of Forming A Vertical Transistor - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 10-23-2014 |
20140346652 | BURIED DIGITLINE (BDL) ACCESS DEVICE AND MEMORY ARRAY - A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench. | 11-27-2014 |
20150014766 | Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings. | 01-15-2015 |
20150037961 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 02-05-2015 |
20150123280 | SILICON BURIED DIGIT LINE ACCESS DEVICE AND METHOD OF FORMING THE SAME - An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches. | 05-07-2015 |
20150206886 | Methods of Forming Memory Arrays and Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material. | 07-23-2015 |
20150255599 | VERTICAL MEMORY DEVICES, MEMORY ARRAYS, AND RELATED METHODS - Vertical memory devices comprise vertical transistors, buried digit lines extending in a first direction in an array region, and word lines extending in a second direction different from the first direction. Portions of the word lines in a word line end region have a first vertical length greater than a second vertical length of portions of the word lines in the array region. Apparatuses including vertical transistors in an array region, buried digit lines extending in a first direction, and word lines are also disclosed. Each of the word lines extends in a second direction perpendicular to the first direction, is formed over at least a portion of a sidewall of at least some of the vertical transistors, and vertically has a depth in a word line end region about equal to or greater than a depth thereof in the array region. | 09-10-2015 |
20150279851 | METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES - 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material. | 10-01-2015 |