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| 20110102731 | LIQUID CRYSTAL MATERIAL, LIQUID CRYSTAL DISPLAY DEVICE, LIQUID CRYSTAL OPTICAL SPACE MODULATION DEVICE, AND LIQUID CRYSTAL SHUTTER - A liquid crystal material in which liquid crystal molecules have uniform alignment state is provided. A liquid crystal layer containing a liquid crystal material is included between a TFT array substrate and an opposed substrate. The liquid crystal material has a phase system continuously showing an isotropic phase, a nematic phase, and a smectic ‘A’ phase in this order as temperature changes from higher state to lower state and shows electroclinic effect in the smectic ‘A’ phase. As the liquid crystal material is heated (temperature is increased), the nematic phase is shown after the smectic ‘A’ phase without other phase in between, and the isotropic phase is shown after the nematic phase without other phase in between. Since the alignment state of the liquid crystal molecules becomes uniform, the transmittance is precisely controlled. | 05-05-2011 |
| 20110310465 | ELECTROPHORETIC DEVICE, DISPLAY, AND ELECTRONIC APPARATUS - An electrophoretic device includes an insulating liquid, an electrophoretic particle in the insulating liquid, and a porous layer in the insulating liquid. The porous layer includes a fibrous structure that includes a non-electrophoretic particle having an optical reflective property different from that of the electrophoretic particle. | 12-22-2011 |
| 20120212798 | ELECTROPHORETIC ELEMENT AND DISPLAY DEVICE - An electrophoretic element includes: an electrophoretic particle; a porous layer formed of a fibrous structure containing a non-migrating particle having optical reflective characteristics different from those of the electrophoretic particle and having a plurality of pores; and a partition that is partially adjacent to the porous layer and defines a space for accommodating the electrophoretic particle. An area rate of the pores per unit area of the porous layer is small in an adjacent region where the partition is adjacent to the porous layer compared with in a non-adjacent region where the partition is not adjacent to the porous layer. | 08-23-2012 |
| 20120243073 | ELECTROPHORETIC ELEMENT, DISPLAY, AND ELECTRONIC DEVICE - An electrophoretic element includes an electrophoretic particle, and a porous layer formed of a fibrous structure having a non-electrophoretic particle with different optical reflection characteristics from optical reflection characteristics of the electrophoretic particle. A difference Δ | 09-27-2012 |
| 20120250138 | ELECTROPHORETIC DEVICE, DISPLAY UNIT, AND ELECTRONIC UNIT - An electrophoretic device includes: an electrophoretic particle; a porous layer formed of a fibrous structure containing a non-electrophoretic particle having optical reflection characteristics different from those of the electrophoretic particle; and a dividing wall adjacent to the porous layer. The electrophoretic particle, the porous layer, and the dividing wall are in an insulating liquid. Volume resistivity of the fibrous structure is larger than volume resistivity of the insulating liquid, and volume resistivity of the dividing wall is larger than the volume resistivity of the insulating liquid. | 10-04-2012 |
| 20120314273 | ELECTROPHORETIC DEVICE, DISPLAY UNIT, AND ELECTRONIC UNIT - An electrophoretic device includes an electrophoretic particle, a porous layer formed of a fibrous structure containing a non-electrophoretic particle having optical reflection characteristics different from optical reflection characteristics of the electrophoretic particle, and a pair of electrodes arranged with the porous layer in between. The porous layer is adjacent to one or both of the pair of electrodes. | 12-13-2012 |
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| 20120148809 | HIGH HARDNESS IMPRINT MATERIAL - There is provided an imprint material from which a film having a high hardness can be formed. An imprint material comprising a component (A), a component (B) and a component (C), the component (A) being a compound having, in the molecule thereof, five or more polymerizable groups, the component (B) being a compound having, in the molecule thereof, two polymerizable groups, and the component (C) being a photo-radical generator. | 06-14-2012 |
| 20130026132 | PLANARIZING FILM-FORMING COMPOSITION FOR HARD DISK AND HARD DISK PRODUCTION METHOD USING SAME - A planarizing film-forming composition for a hard disk that is a non-magnetic filler is sufficiently filled into fine grooves on a magnetic material surface (surface), and is required not to cause contraction in the filled parts at the time of photo-curing (at the time of exposure) and post-exposure baking; and a method for producing a hard disk using the composition. The composition comprising at least one polyfunctional (meth)acrylate compound being in a liquid state at room temperature and atmospheric pressure and having a molecular weight of 300 to 10,000. The compound preferably has 2 to 20 (meth)acrylate groups in the molecule, or the compound preferably has a molecular weight of 300 to 2,300. A method for producing a hard disk comprising: forming a concave-convex shape on the surface; covering the surface having the concave-convex shape with the composition; and etching the covered surface for planarization until the surface is exposed. | 01-31-2013 |
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| 20100040697 | COSMETIC PRODUCT, NANOPARTICLES FOR COSMETICS, AND POWDER FOR COSMETICS - The invention provides a cosmetic product which has a good texture and allows full expression of the inherent functions of ceramide as an intercellular lipid, such as skin barrier function and hair protection effect, as well as nanoparticles for cosmetics and powder for cosmetics which may be used in the above cosmetic product, exhibit good skin barrier function and hair protection effect, and are easy to incorporate into the above cosmetic product. The cosmetic product, the nanoparticles, and the powder for cosmetics according to the present invention contain a polymer obtained by polymerization of a monomer material containing a glycerol (meth)acrylate monomer represented by the formula (1): | 02-18-2010 |
| 20120276179 | COSMETIC PRODUCT, NANOPARTICLES FOR COSMETICS, AND POWDER FOR COSMETICS - The invention provides a cosmetic product which has a good texture and allows full expression of the inherent functions of ceramide as an intercellular lipid, such as skin barrier function and hair protection effect, as well as nanoparticles for cosmetics and powder for cosmetics which may be used in the above cosmetic product, exhibit good skin barrier function and hair protection effect, and are easy to incorporate into the above cosmetic product. The cosmetic product, the nanoparticles, and the powder for cosmetics according to the present invention contain a polymer obtained by polymerization of a monomer material containing a glycerol(meth)acrylate monomer represented by the formula (1): | 11-01-2012 |
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| 20080219038 | FERROELECTRIC MEMORY DEVICE - Disclosed is a ferroelectric memory device. Multiple memory cells are connected between bit lines and a plate line, and constitute a memory cell array. Each of the memory cells is composed of a first ferroelectric capacitor and a memory cell transistor. The gates of the memory cell transistors are connected to multiple word lines, respectively. The bit lines are connected to multiple sense amplifiers for amplifying information. One end of the second ferroelectric capacitor is electrically connected to a corresponding one of the bit lines, and the other end of the second ferroelectric capacitor is electrically connected to a power supply. | 09-11-2008 |
| 20130058161 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a first memory region; and a second memory region. The transistor controls a conduction of each of a current flowing between the first and the second signal lines and an opposite current. The first memory region has a first magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and the magnetization direction becomes antiparallel when a current in another direction. The second memory region has a second magnetic tunnel junction element. A magnetization direction thereof becomes parallel when a current flows in one direction, and becomes antiparallel when a current flows in another first direction. | 03-07-2013 |
| 20130058162 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor. | 03-07-2013 |
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| 20090059648 | FERROELECTRIC SEMICONDUCTOR STORAGE DEVICE - This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the transistor. A bit line is connected to the other electrode of a capacitor and the other end of the transistor, the capacitor having its one electrode connected to the ground. A bit line potential detection circuit detects a potential of the bit line. A connection circuit provides the same potential between a potential of the plate line and a potential of the bit line based on an output from the bit line potential detection circuit. | 03-05-2009 |
| 20090219748 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory includes ferroelectric capacitors including ferroelectric films between first electrodes and second electrodes; cell transistors; and a bit line contact connecting the cell transistors to a bit line, wherein the first electrode is connected to one of source and drain of the cell transistor at a first node, so that the ferroelectric capacitor and the cell transistor form a unit cell, the other of source and drain of the cell transistor for the unit cell is connected to the first node of other unit cell to serially connect the cell transistors for unit cells, so that the unit cells form a cell string, the word lines are connected to gates of the cell transistors or function as gates, the plate lines are connected to the second electrodes of the ferroelectric capacitors, and the bit line is connected to a cell transistor at an end of the cell string. | 09-03-2009 |
| 20100020588 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes cell blocks configured to have a plurality of memory cells connected in series, each memory cell comprising a ferroelectric capacitor and a cell transistor connected in parallel with each other; word lines connected to gates of a plurality of the cell transistors; block selectors connected to first ends of the cell blocks; bit lines connected to the first ends of the cell blocks via the block selectors; and plate lines connected to second ends of the cell blocks, wherein the first ends of first and second cell blocks of the cell blocks respectively sharing the word lines are connected to the same bit line via the block selectors different from each other, and the second ends of the first and the second cell blocks respectively are connected to the plate lines different from each other. | 01-28-2010 |
| 20100073986 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of cell blocks each of which is configured by serially connecting a plurality of memory cells each of which comprises a ferroelectric capacitor and a cell transistor connected in parallel; a plurality of word lines connected to gates of the cell transistors; a plurality of block selectors each of which comprises an enhancement transistor and a depletion transistor serially connected to each other; a plurality of bit lines connected via the block selectors to one ends of the cell blocks; and a plurality of plate lines connected to the other ends of the cell blocks, wherein a gate length of the enhancement transistor is longer than that of the depletion transistor. | 03-25-2010 |
| 20110018043 | SEMICONDUCTOR MEMORY DEVICE - A memory includes first contact plugs; ferroelectric capacitors above the first contact plugs; second contact plugs in a first interlayer film being below an area which is between two adjacent ferroelectric capacitors, the second contact plug; first interconnections connected to the second contact plugs, the first interconnections extending in a first direction substantially perpendicular to an arrangement direction, in which the two ferroelectric capacitors are arranged, on the first interlayer film; a second interlayer film above the first interlayer film and the first interconnection; third contact plugs in the second interlayer film, the third contact plugs being respectively connected to the first interconnections at positions shifted from the second contact plugs in the first direction; and second interconnections electrically connecting the third contact plug to the upper electrodes of the two ferroelectric capacitors. | 01-27-2011 |
| 20110266600 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to embodiments includes a semiconductor substrate and plural switching transistors provided on the semiconductor substrate. In the semiconductor memory device, a contact plug is embedded between adjacent two of the switching transistors, and is insulated from gates of the adjacent two switching transistors. The contact plug is also electrically connected to a source or a drain of each of the adjacent two switching transistors, and an upper surface of the contact plug is at a position higher than an upper surface of the switching transistors. A memory element is provided on the upper surface of the contact plug and stores data. A wiring is provided on the memory element. | 11-03-2011 |
| 20120153414 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes: a plurality of magnetic tunnel junction elements arranged on a semiconductor substrate; and a plurality of selection transistors electrically connected to first ends of the plurality of magnetic tunnel junction elements. A plurality of first bit lines are respectively connected to the first ends of the magnetic tunnel junction elements via one or more of the selection transistors. A plurality of upper electrodes are respectively connected to second ends of the plurality of magnetic tunnel junction elements. A plurality of second bit lines are respectively connected to the second ends of the magnetic tunnel junction elements via the upper electrodes. The upper electrodes extend along the second bit lines, and one of the upper electrodes is commonly connected to the second ends of the plurality of magnetic tunnel junction elements arranged in an extending direction of the second bit lines. | 06-21-2012 |
| 20120243303 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting state when a current is allowed to flow through the magnetic tunnel junction element. A current limiter limits a current flowing through the cell transistor and the magnetic tunnel junction element upon data writing. | 09-27-2012 |
| 20120314469 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a semiconductor substrate and an active area on the semiconductor substrate. A plurality of cell transistors are formed on the active area. A first bit line and a second bit line are paired with each other. A plurality of word lines intersect the first and second bit lines. A plurality of storage elements respectively has a first end electrically connected to a source or a drain of one of the cell transistors and a second end connected to the first or second bit line. Both of the first and second bit lines are connected to the same active area via the storage elements. | 12-13-2012 |
| 20120314494 | SEMICONDUCTOR STORAGE DEVICE - In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines. | 12-13-2012 |
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| 20110095185 | SEMICONDUCTOR INSPECTING APPARATUS - In the case of inspecting samples having different sizes by means of a semiconductor inspecting apparatus, a primary electron beam bends since distribution is disturbed on an equipotential surface at the vicinity of the sample at the time of inspecting vicinities of the sample, and what is called a positional shift is generated. A potential correcting electrode is arranged outside the sample and at a position lower than the sample lower surface, and a potential lower than that of the sample is applied. Furthermore, a voltage to be applied to the potential correcting electrode is controlled corresponding to a distance between the inspecting position and a sample outer end, sample thickness and irradiation conditions of the primary electron beam. | 04-28-2011 |
| 20110303844 | ELECTRON MICROSCOPE, AND SPECIMEN HOLDING METHOD - It is an object of the present invention to provide an electron microscope for properly applying a retarding voltage to a sample which is brought into electrical conduction. | 12-15-2011 |
| 20120261589 | SEMICONDUCTOR INSPECTING APPARATUS - In the case of inspecting samples having different sizes by means of a semiconductor inspecting apparatus, a primary electron beam bends since distribution is disturbed on an equipotential surface at the vicinity of the sample at the time of inspecting vicinities of the sample, and what is called a positional shift is generated. A potential correcting electrode is arranged outside the sample and at a position lower than the sample lower surface, and a potential lower than that of the sample is applied. Furthermore, a voltage to be applied to the potential correcting electrode is controlled corresponding to a distance between the inspecting position and a sample outer end, sample thickness and irradiation conditions of the primary electron beam. | 10-18-2012 |
