Patent application number | Description | Published |
20100322018 | Temperature Compensation Circuit and Method for Sensing Memory - A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot. | 12-23-2010 |
20110128786 | MEMORY DEVICE - A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source. | 06-02-2011 |
20120063232 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 03-15-2012 |
20120063236 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 03-15-2012 |
20120155181 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 06-21-2012 |
20120163087 | Decoder for Nand Memory - An integrated circuit device has multiple blocks of NAND memory cells, and a high voltage switch. The high voltage switch is coupled to a decoder output and the blocks of NAND memory cells. The high voltage switch has an output voltage range with positive and negative voltages. | 06-28-2012 |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 10-18-2012 |
20130114341 | Method and Apparatus for Indicating Bad Memory Areas - Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled. | 05-09-2013 |
20130176781 | 3D Memory Array with Read Bit Line Shielding - A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines. | 07-11-2013 |
20130208548 | Method and Apparatus for Copying Data With A Memory Array Having Redundant Memory - A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the columns of the main array and the set of redundant columns of the redundant array into, for example, sets of rows. The copy back programming transfers data from a part of the source page in the redundant array to a part of the destination page in the main array, and transfers data from a part of the source page in the main array to a part of the destination page in the redundant array. | 08-15-2013 |
20140056072 | 3D MEMORY ARRAY WITH READ BIT LINE SHIELDING - A memory device includes a block of memory cells having a plurality of levels. Each level includes strips of memory cells extending in a first direction between first and second ends of the block. A first bit line structure, at each level at the first end, is coupled to a first string of memory cells extending from the first end. A second bit line structure, at each level at the second end, is coupled to a second string of memory cells extending from said second end. Bit line pairs extend in the first direction with each including odd and even bit lines. Odd and even bit line connectors connect the odd and even bit lines to the second and first bit line structures, respectively. Each bit line for a series of bit line pairs are separated by a bit line of an adjacent pair of bit lines. | 02-27-2014 |
20140098616 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 04-10-2014 |
20140160849 | METHOD AND APPARATUS FOR INDICATING BAD MEMORY AREAS - Regardless of data values stored on data memory cells, all read operations on the data memory cells are disallowed. For example, current flow is disallowed through a string of the data memory cells and one or more select line memory cells. The particular select value stored in a first select line memory cell in the string, for example coupled to a ground select line or a string select line, determines whether the string is enabled or disabled. | 06-12-2014 |
20140254260 | REDUCING COUPLING NOISE DURING READ OPERATION - A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level V | 09-11-2014 |
20140254284 | WORD LINE DRIVER CIRCUIT FOR SELECTING AND DESELECTING WORD LINES - A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage. | 09-11-2014 |
20140254297 | METHOD AND APPARATUS FOR MEMORY REPAIR - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 09-11-2014 |
20140258811 | STORAGE SCHEME FOR BUILT-IN ECC OPERATIONS - A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations. | 09-11-2014 |
20140269074 | MANAGEMENT OF NON-VOLATILE MEMORY - A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged. | 09-18-2014 |
20140281175 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 09-18-2014 |