Patent application number | Description | Published |
20130299886 | Backside Structure and Methods for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 11-14-2013 |
20130299931 | Backside Structure for BSI Image Sensor - An embodiment method for forming an image sensor includes forming an anti-reflective coating over a surface of a semiconductor supporting a photodiode, forming an etching stop layer over the anti-reflective coating, forming a buffer oxide over the etching stop layer, and selectively removing a portion of the buffer oxide through etching, the etching stop layer protecting the anti-reflective coating during the etching. An embodiment image sensor includes a semiconductor disposed in an array region and in a periphery region, the semiconductor supporting a photodiode in the array region, an anti-reflective coating disposed over a surface of the semiconductor, an etching stop layer disposed over the anti-reflective coating, a thickness of the etching stop layer over the photodiode in the array region less than a thickness of the etching stop layer in the periphery region, and a buffer oxide disposed over the etching stop layer in the periphery region. | 11-14-2013 |
20130307107 | BSI Image Sensor Chips with Separated Color Filters and Methods for Forming the Same - A device includes a semiconductor substrate having a front side and a backside. A plurality of image sensors is disposed at the front side of the semiconductor substrate. A plurality of clear color-filters is disposed on the backside of the semiconductor substrate. A plurality of metal rings encircles the plurality of clear color-filters. | 11-21-2013 |
20140077320 | Scribe Lines in Wafers - A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines includes a metal-feature containing scribe line comprising metal features therein, and a metal-feature free scribe line parallel to, and adjoining, the metal-feature containing scribe line. A second plurality of scribe lines is between the columns of the plurality of chips. | 03-20-2014 |
20140159190 | Backside Structure and Methods for BSI Image Sensors - BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. | 06-12-2014 |
20140199804 | SEMICONDUCTOR DEVICE HAVING A BONDING PAD AND SHIELD STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of fabricating a semiconductor device includes providing a device substrate having a front side and a back side corresponding to a front side and a back side of the semiconductor device, forming, on the front side of the device substrate, a metal feature, forming, on the back side of the device substrate, an insulating layer, forming, on the back side of the semiconductor device, a trench exposing the metal feature, forming a bonding pad in the trench in electrical communication with the metal feature, and forming, on the insulating layer, a metal shield, in which the metal shield and the bonding pad have different thicknesses relative to each other. | 07-17-2014 |
20140231949 | IMAGE SENSOR FOR MITIGATING DARK CURRENT - One or more embodiments of techniques or systems for mitigating dark current of an image sensor are provided herein. Generally, a silicon interface, such as an edge of a dielectric region or an edge between a back side interface (BSI) region and a pass region, is a source of electrons or holes which cause dark current. In some embodiments, the image sensor includes a surface protect region. For example, the surface protect region is doped with a first doping type and a photo-diode of the image sensor is doped with the same first doping type. In this manner, the surface protect region acts as an electron magnet or a hole magnet for electrons or holes from the silicon interface, thus mitigating electrons or holes from the silicon interface from being collected by the photo-diode, for example. | 08-21-2014 |
20140252521 | Image Sensor with Improved Dark Current Performance - Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate having a first side and a second side opposite the first side. The semiconductor substrate contains a radiation-sensing region configured to sense radiation projected toward the substrate from the second side. A first layer is disposed over the second side of the semiconductor substrate. The first layer has a first energy band gap. A second layer is disposed over the first layer. The second layer has a second energy band gap. A third layer is disposed over the second layer. The third layer has a third energy band gap. The second energy band gap is smaller than the first energy band gap and the third energy band gap. | 09-11-2014 |
20140252523 | Backside Structure and Methods for BSI Image Sensors - A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern. | 09-11-2014 |
20140264504 | Method and Apparatus for Low Resistance Image Sensor Contact - A method and apparatus for a low resistance image sensor contact, the apparatus comprising a photosensor disposed in a substrate, a first ground well disposed in a first region of the substrate, the first ground well having a resistance lower than the substrate, and a ground line disposed in a region adjacent to the first ground well. The first ground well is configured to provide a low resistance path to the ground line from the substrate for excess free carriers in the first region of the substrate. The apparatus may optionally comprise a second ground well having a lower resistance than the first ground well and disposed between the first ground well and the ground line, and may further optionally comprise a third ground well having a lower resistance than the second ground well and disposed between the second ground well and the ground line. | 09-18-2014 |
20140264508 | Structure and Method for 3D Image Sensor - The present disclosure provides an embodiment of an image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors. | 09-18-2014 |
20140264683 | Imaging Sensor Structure and Method - The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors. | 09-18-2014 |
20140264862 | Interconnect Structure and Method - A semiconductor device comprises a first semiconductor chip including a first substrate and a plurality of first metal lines formed over the first substrate and a second semiconductor chip bonded on the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate and a plurality of second metal lines formed over the second substrate. The semiconductor device further comprises a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion formed over a first side of a hard mask layer, wherein the first portion is of a first width and a second portion formed over a second side of the hard mask layer, wherein the second portion is of a second width greater than or equal to the first width. | 09-18-2014 |