Patent application number | Description | Published |
20080305624 | Bonding Structure With Buffer Layer And Method Of Forming The Same - A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated. | 12-11-2008 |
20100230803 | ELECTRONIC DEVICE PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a method for forming an electronic device package, which includes providing a carrier substrate having an upper surface and an opposite lower surface; forming a cavity from the upper surface of the carrier substrate; disposing an electronic device having a conducting electrode in the cavity; forming a filling layer in the cavity, wherein the filling layer surround the electronic device; thinning the carrier substrate from the lower surface to a predetermined thickness; forming at least a through-hole in the electronic device or the in the carrier substrate; and forming a conducting layer over a sidewall of the through-hole, wherein the conducting layer electrically connects to the conducting electrode. | 09-16-2010 |
20100289092 | POWER MOSFET PACKAGE - A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. | 11-18-2010 |
20110042819 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer. | 02-24-2011 |
20110084382 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed. | 04-14-2011 |
20110127670 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip. | 06-02-2011 |
20110233782 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed. | 09-29-2011 |
20120241923 | IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME - An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process. | 09-27-2012 |
20140154840 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole. | 06-05-2014 |