Patent application number | Description | Published |
20080258234 | SEMICONDUCTOR STRUCTURE FOR LOW PARASITIC GATE CAPACITANCE - A semiconductor structure provides lower parasitic capacitance between the gate electrode and contact vias while providing substantially the same level of stress applied by a nitride liner as conventional MOSFETs by reducing the height of the gate electrode and maintaining substantially the same height for the gate spacer. The nitride liner contacts only the outer sidewalls of the gate spacer, while not contacting inner sidewalls, or only a small area of the inner sidewalls of the gate spacer, therefore applying substantially the same level of stress to the channel of the MOSFET as conventional MOSFETs. The volume surrounded by the gate spacer and located above the gate electrode is either filled with a low-k dielectric material or occupied by a cavity having a dielectric constant of substantially 1.0. The reduced height of the gate electrode and the low-k dielectric gate filler or the cavity reduces the parasitic capacitance. | 10-23-2008 |
20080290409 | HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL - Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes. | 11-27-2008 |
20080303105 | DUAL GATE DIELECTRIC SRAM - An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance. | 12-11-2008 |
20090007051 | SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES - A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option. | 01-01-2009 |
20090072312 | Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS - A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack. | 03-19-2009 |
20090108302 | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES - A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may comprise a performance sensitive logic device and the second device may comprise a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices. | 04-30-2009 |
20090146223 | PROCESS AND METHOD TO LOWER CONTACT RESISTANCE - A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface. | 06-11-2009 |
20090148988 | METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING - Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET. | 06-11-2009 |
20090155969 | PROTECTION OF SIGE DURING ETCH AND CLEAN OPERATIONS - A method of making a semiconductor device includes forming a transistor structure having one of an embedded epitaxial stressed material in a source and drain region and a stressed channel and well, subjecting the transistor structure to plasma oxidation, and removing spacer material from the transistor structure. | 06-18-2009 |
20090177448 | COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE - A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature. | 07-09-2009 |
20090178012 | METHODOLOGY FOR IMPROVING DEVICE PERFORMANCE PREDICTION FROM EFFECTS OF ACTIVE AREA CORNER ROUNDING - A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics. | 07-09-2009 |
20090294854 | HALO-FIRST ULTRA-THIN SOI FET FOR SUPERIOR SHORT CHANNEL CONTROL - Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes. | 12-03-2009 |
20090302386 | SOI TRANSISTOR HAVING A CARRIER RECOMBINATION STRUCTURE IN A BODY - A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor. | 12-10-2009 |
20090315138 | METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE - In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. | 12-24-2009 |
20100112766 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions. | 05-06-2010 |
20100159684 | Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS - A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack. | 06-24-2010 |
20100197118 | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES - A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices. | 08-05-2010 |
20110027956 | Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 02-03-2011 |
20110079851 | SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS - Disclosed is an SOI device on a bulk silicon layer which has an FET region, a body contact region and an STI region. The FET region is made of an SOI layer and an overlying gate. The STI region includes a first STI layer separating the SOI device from an adjacent SOI device. The body contact region includes an extension of the SOI layer, a second STI layer on the extension and a body contact in contact with the extension. The first and second STI layers are contiguous and of different thicknesses so as to form a split level STI. | 04-07-2011 |
20110225562 | COMPACT MODEL METHODOLOGY FOR PC LANDING PAD LITHOGRAPHIC ROUNDING IMPACT ON DEVICE PERFORMANCE - A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance. Then, transistor model parameter values in a transistor compact model are updated for the transistor device to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a device simulation may then include the deltaW adder values to quantify the influence of the lithographic rounding effect of the landing pad feature. | 09-15-2011 |
20120037880 | Contacts for Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact. | 02-16-2012 |
20120068150 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. | 03-22-2012 |
20120112280 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 05-10-2012 |
20120180010 | METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 07-12-2012 |
20120184075 | REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION - A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail. | 07-19-2012 |
20120280205 | Contacts for Nanowire Field Effect Transistors - A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region. | 11-08-2012 |
20120329217 | Nanowire Field Effect Transistors - A method for forming a nanowire field effect transistor (FET) device including forming a first silicon on insulator (SOI) pad region, a second SOI pad region, a third SOI pad region, a first SOI portion connecting the first SOI pad region to the second SOI pad region, and a second SOI portion connecting the second SOI pad region to the third SOI pad region on a substrate, patterning a first hardmask layer over the second SOI portion, forming a first suspended nanowire over the semiconductor substrate, forming a first gate structure around a portion of the first suspended nanowire, patterning a second hardmask layer over the first gate structure and the first suspended nanowire, removing the first hardmask layer, forming a second suspended nanowire over the semiconductor substrate, forming a second gate structure around a portion of the second suspended nanowire, and removing the second hardmask layer. | 12-27-2012 |
20130087787 | ELECTRICAL MASK INSPECTION - An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain. | 04-11-2013 |
20130087859 | Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 04-11-2013 |
20130093040 | SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG - A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates. | 04-18-2013 |
20130105894 | THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS | 05-02-2013 |
20130105896 | Threshold Voltage Adjustment For Thin Body Mosfets | 05-02-2013 |
20130126986 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 05-23-2013 |
20130168776 | Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 07-04-2013 |
20130221319 | Gate-All Around Semiconductor Nanowire FET's On Bulk Semicoductor Wafers - Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate. | 08-29-2013 |
20130221328 | Pad-Less Gate-All Around Semiconductor Nanowire FETs On Bulk Semiconductor Wafers - A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region. | 08-29-2013 |
20130224915 | GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETs ON BULK SEMICONDUCTOR WAFERS - Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate. | 08-29-2013 |
20130224924 | PAD-LESS GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETS ON BULK SEMICONDUCTOR WAFERS - A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire. | 08-29-2013 |
20130328124 | GATED DIODE STRUCTURE FOR ELIMINATING RIE DAMAGE FROM CAP REMOVAL - A semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics. | 12-12-2013 |
20140061819 | GERMANIUM OXIDE FREE ATOMIC LAYER DEPOSITION OF SILICON OXIDE AND HIGH-K GATE DIELECTRIC ON GERMANIUM CONTAINING CHANNEL FOR CMOS DEVICES - A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region. | 03-06-2014 |
20140084412 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. | 03-27-2014 |
20140103457 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 04-17-2014 |
20140106531 | FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK - A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure. | 04-17-2014 |
20140106550 | ION IMPLANTATION TUNING TO ACHIEVE SIMULTANEOUS MULTIPLE IMPLANT ENERGIES - A method of ion implantation is disclosed. A beam of ions is accelerated to a first energy level. The beam of ions is decelerated from the first energy level to produce a contamination beam of ions via an ion collision process. The ions of the contamination beam are implanted in a substrate to obtain a selected dopant profile in the substrate. | 04-17-2014 |
20140117409 | METHOD AND STRUCTURE FOR BODY CONTACTED FET WITH REDUCED BODY RESISTANCE AND SOURCE TO DRAIN CONTACT LEAKAGE - A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region. | 05-01-2014 |
20140203359 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 07-24-2014 |
20140206160 | Method of Forming A Gated Diode Structure for Eliminating RIE Damage From Cap Removal - A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-K gate stack made of non-silicided gate material, the gated-diodes being adjacent to FETs, each of which having a silicided source, a silicided drain and a silicided HiK gate stack. The semiconductor structure eliminates a cap removal RIE in a gate first High-K metal gate flow from the region of the gated-diode. The lack of silicide and the presence of a nitride barrier on the gate of the diode are preferably made during the gate first process flow. The absence of the cap removal RIE is beneficial in that diffusions of the diode are not subjected to the cap removal RIE, which avoids damage and allows retaining its highly ideal junction characteristics. | 07-24-2014 |
20140246727 | WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 09-04-2014 |
20140252539 | PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION - A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections. | 09-11-2014 |
20140264558 | FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. | 09-18-2014 |
20140349451 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR - A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region. | 11-27-2014 |
20150054080 | SHALLOW TRENCH ISOLATION STRUCTURE HAVING A NITRIDE PLUG - A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates. | 02-26-2015 |
20150084096 | FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS - A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects. | 03-26-2015 |
20150084132 | Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors - Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained. | 03-26-2015 |