Patent application number | Description | Published |
20090278716 | SAMPLE HOLD CIRCUIT FOR USE IN TIME-INTERLEAVED A/D CONVERTER APPARATUS INCLUDING PARALLELED LOW-SPEED PIPELINE A/D CONVERTERS - A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor. | 11-12-2009 |
20100073214 | DIFFERENTIAL OPERATIONAL AMPLIFIER CIRCUIT CORRECTING SETTLING ERROR FOR USE IN PIPELINED A/D CONVERTER - A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region. | 03-25-2010 |
20110031543 | IMAGING DEVICE BY BURIED PHOTODIODE STRUCTURE - An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected. | 02-10-2011 |
20110193553 | Magnetic array sensor circuit to process an output from a magnetic sensor array - A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array. | 08-11-2011 |
20120127004 | A/D CONVERSION INTEGRATED CIRCUIT - An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter | 05-24-2012 |
20120193692 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering. | 08-02-2012 |
20120193743 | SEMICONDUCTOR ELEMENT AND SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges. | 08-02-2012 |
20120301150 | OPTICAL-INFORMATION ACQUIRING ELEMENT, OPTICAL INFORMATION ACQUIRING ELEMENT ARRAY, AND HYBRID SOLID-STATE IMAGING DEVICE - A optical-information acquisition element encompasses a semiconductor layer ( | 11-29-2012 |
20130044247 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF READING PIXEL SIGNAL, AND PIXEL - In a pixel | 02-21-2013 |
20130057418 | PIPELINED A/D CONVERTER CIRCUIT PROVIDED WITH A/D CONVERTER CIRCUIT PARTS OF STAGES EACH INCLUDING PRECHARGE CIRCUIT - A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal. | 03-07-2013 |
20130120180 | A/D CONVERTER - An A/D converter | 05-16-2013 |
20140014821 | A/D CONVERTER, IMAGE SENSOR DEVICE, AND METHOD OF GENERATING DIGITAL SIGNAL FROM ANALOG SIGNAL - According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration. | 01-16-2014 |
20140232917 | SOLID STATE IMAGE PICK-UP DEVICE, AND PIXEL | 08-21-2014 |
20140319325 | LAMP SIGNAL GENERATION CIRCUIT AND CMOS IMAGE SENSOR - A ramp signal generation circuit | 10-30-2014 |