Patent application number | Description | Published |
20100157645 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 06-24-2010 |
20110051351 | Circuit board, semiconductor device including the same, memory module, memory system, and manufacturing method of circuit board - A circuit board according to the present invention includes a main surface, a back surface parallel to the main surface, a side surface positioned between edges of the main surface and the back surface, and first and second board terminals covering a portion of the main surface and a portion of the side surface, respectively. According to the present invention, because the board terminals are provided not only on the main surface but also on the side surface of the circuit board, the total number of board terminals can be increased while maintaining sufficient pitch and width of the board terminals. | 03-03-2011 |
20110093764 | MEMORY MODULE ON WHICH REGULAR CHIPS AND ERROR CORRECTION CHIPS ARE MOUNTED - Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area. | 04-21-2011 |
20120026772 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 02-02-2012 |
20120281348 | MEMORY MODULE AND LAYOUT METHOD THEREFOR - The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector. | 11-08-2012 |
20130063998 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 03-14-2013 |
20130147042 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias. | 06-13-2013 |
20140286074 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 09-25-2014 |