Patent application number | Description | Published |
20100002703 | Packet Relay Device And Method For Transferring Packet Therein - A packet relay device receives an input packet via a first communication port out of a plurality of communication ports of the packet relay device and transmits the input packet via a second communication port out of the plurality of communication ports. The packet relay device includes a learning table storage, a header adder, a discard determiner, and a packet reducer. The learning table storage stores a source address contained in the input packet, in association with an input port identifier capable of identifying the first communication port. The header adder adds an internal transfer header containing the input port identifier to the input packet to generate an internal transfer packet. The discard determiner determines whether to discard the internal transfer packet. The packet reducer reduces the internal transfer packet to preserve at least the source address and the input port identifier upon determining to discard the internal transfer packet. | 01-07-2010 |
20100014539 | Packet Relay Device And Queue Scheduling Method - Each of the plurality of queues stores packet data of a received packet. The read concession assignor assigns one of the plurality of queues with a read concession for a predefined time period. The overdraft storage stores an overdraft amount in connection with each of the plurality of queues. The read adequacy determiner determines, in accordance with an overdraft amount stored in connection with one queue out of the plurality of queues, whether to read packet data from the one queue. The overdraft updater updates at least one of a first overdraft amount stored in connection with a first queue and a second overdraft amount stored in connection with a second queue different from the first queue upon reading packet data from the first queue during a time period while the second queue is assigned with the read concession. | 01-21-2010 |
20110296284 | Transmission apparatus and parity calculation method - In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity calculation controller calculates the parity by the frame and inserts a calculation result into a next frame to a second frame sequence. The second parity calculation controller receives from the first parity calculation controller first parity data which is a parity calculation result by the first parity calculation controller and which has the same value as that of a parity calculation result to be inserted into a target frame of a parity calculation in the second frame sequence. Then, the controller calculates the parity of the target frame including the first parity data and second parity data which is a parity calculation result of a previous frame in the second frame sequence before one frame of the target frame. | 12-01-2011 |
Patent application number | Description | Published |
20090113234 | VIRTUALIZATION SWITCH AND METHOD FOR CONTROLLING A VIRTUALIZATION SWITCH - A virtualization switch includes first communication line connection terminals which can be connected to a host computer, a physical storage apparatus or a plurality of physical storage apparatuses, and another virtualization switch, a second communication line connection terminal which can be connected to a single line concentrator or a plurality of line concentrators connected to a manager computer by a second communication line a storage virtualization unit, a first communication unit which can communicate with an other virtualization switch through a first communication line, second communication unit which can communicate with the other virtualization switch through an second communication line, second communication line monitor unit which test communication between the virtualization switch, and abnormal state coping unit which executes a closing process and causes the first communication unit to output a failover designation instruction. | 04-30-2009 |
20090198745 | VIRTUALIZATION SWITCH, COMPUTER SYSTEM, AND DATA COPY METHOD - A virtualization switch connected to a host computer and a plurality of physical storage devices includes a plurality of communication line connection terminals and storage virtualizing unit allowing the host computer to recognize a storage area generated by combining some or all of storage areas of the plurality of physical storage devices as a virtual storage device, a plurality of copy process unit copying data in the storage area, and control unit controlling a copy process operation by assigning copy sessions based on instructions from the host computer to the plurality of copy process unit. When the number of copy process units is larger than number of copy sessions, the control unit performs control to distribute part of a copy process in the one or copy process units that are currently performing the copy process to the one or more copy process units that are not performing the copy process. | 08-06-2009 |
20100030988 | VIRTUALIZING SWITCH AND COMPUTER SYSTEM - A virtualizing switch includes a storage virtualizing section for making the host computer recognize storage areas prepared by combining storage areas of a physical storage devices as virtual storage devices, a data copying section for executing data copying between the virtual storage devices, a range locking section for dividing a storage area for storing data to be copied of a virtual storage device of a copy source into storage area parts having a previously set division size and inhibiting access to a divided storage area part, an instruction number counting section for counting the number of access instructions to the divided storage area part that is inhibited by the range locking section, and a divided capacity changing section for changing the division size based on the number of instructions counted by the instruction number counting section. | 02-04-2010 |
20100058014 | SWITCH APPARATUS - A switch connectable between hosts and storage device, the switch for providing a service of allotting virtual areas to be deployed in the storage device to any of the hosts upon demand, the switch includes: a processor for controlling allotment of virtual areas to the hosts and allocation of physical areas of the storage device to the virtual areas; and a memory for storing information of the host allowed access to the virtual areas, the processor controlling access by any of the hosts to the virtual area so as to restrict access by any of the hosts to a part of the virtual areas allotted to the any of the hosts in reference to the memory. | 03-04-2010 |
20100306492 | Relay device and relay program - Relay devices each include a port connected to a communication channel that is used to transfer and receive an access request to and from another relay device; a first virtual area section that is set as a virtual memory area that receives an access request; and a second virtual area section set as a virtual memory area for receiving an access request transferred from another relay device. The relay device sends, if a channel to a storage device is in operation, the access request that is sent to the first virtual area section and the access request that is sent to the second virtual area section, to the storage device via the channel. The relay device transfers, if the channel is not in operation, the access request sent to the first virtual area section, to another relay device via the communication channel connected to the port. | 12-02-2010 |
20100332772 | APPARATUS, COMPUTER-READABLE RECORDING MEDIUM AND STORAGE SYSTEM - A apparatus for controlling a first storage and a second storage, has a controller for receiving a write command and a read command sent out from a host and for sending out the write command and the read command to the first storage and the second storage, a determining unit for sending out a request corresponding to the write command to the first storage and the second storage, for receiving a first response corresponding to the request from the first storage and a second response corresponding to the request from the second storage, and for determining one of the storages on the basis of each of response times, a first writing unit for writing data into the determined storage, and a second writing unit for writing the data written in the determined storage into the other storage after writing the data into the determined storage by the first writing unit. | 12-30-2010 |
20110191519 | SWITCHING DEVICE, SWITCH CONTROL METHOD, AND STORAGE SYSTEM - A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk. | 08-04-2011 |
20110197091 | SWITCH DEVICE, SWITCH CONTROL METHOD AND STORAGE SYSTEM - A switch device includes a memory unit for storing therein an error response for each error event to be sent in response at the time of a failure with respect to a control signal that controls a storage device connected to the switch device, an error response output unit for receiving input of the control signal and sequentially outputting each error response stored in the memory unit, an operation information computing unit for detecting an operation of a calculating device, which is connected to the switch device, corresponding to each error response output by the error response output unit and for obtaining, as operation information, a condition defining the operation of the calculating device upon receiving each error response, and an operation setting unit for setting operation condition at the time of a failure based on the operation information. | 08-11-2011 |
Patent application number | Description | Published |
20100188912 | SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA - A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line. | 07-29-2010 |
20130077424 | SEMICONDUCTOR MEMORY CIRCUIT AND CONTROL METHOD FOR READING DATA - A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line. | 03-28-2013 |
Patent application number | Description | Published |
20130243114 | TRANSMISSION APPARATUS, TRANSMISSION METHOD AND METHOD OF ALTERING TRANSMISSION BAND - A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation. | 09-19-2013 |
20130259476 | TRANSMISSION METHOD AND NODE DEVICE - A transmission method for transmitting a lower-speed signal transmission frame using a node device in a network by accommodating the lower-speed signal transmission frame into time slots of a higher-speed signal transmission frame includes supplying, when a number of the time slots accommodating the lower-speed signal transmission frame is to be increased, the time slots to input numbers of a cross-connection part of the node device in accordance with an order of time slot numbers of the time slots; and re-establishing cross-connections where the input numbers are cross-connected to corresponding output numbers of the cross-connection part so that the cross-connections are prevented from crossing each other, wherein the input numbers input the time slots and the output numbers output the time slots. | 10-03-2013 |
20130259484 | DATA TRANSMISSION APPARATUS AND DATA TRANSMISSION METHOD - A data transmission device where a low-speed signal transmission frame is included in time slots of a high-speed signal transmission frame and a number of the time slots to include the low-speed signal transmission frame is variable, wherein the time slots have respective time slot numbers, includes a storage unit storing signal data of the high-speed signal transmission frame corresponding to the number of the time slots based on a time slot number basis, wherein the signal data of the high-speed signal transmission frame are supplied on the time slot number basis; and a selection and output unit selecting and sequentially outputting the signal data on the time slot number basis, wherein the signal data have been stored in accordance with the number of the time slots. | 10-03-2013 |
20140119733 | FRAME CONVERTER AND FRAME CONVERSION METHOD - There is provided a frame converter that writes input data included in an input frame to a buffer to accumulate the input data and outputs data read from the buffer as output data included in an output frame, the frame converter includes a setting unit configured to set a time interval from start of resizing of data rate of the input data to start of resizing of data rate of the output data when resizing of an accumulation amount in the buffer is performed in which data rates of the input data and the output data vary, and an adjustment unit configured to adjust to approximate the data rate of the output data to the data rate of the input data after the time interval has elapsed since the start of resizing of data rate of the input data. | 05-01-2014 |
20150132012 | TRANSMISSION APPARATUS - A transmission apparatus includes: a plurality of logical lanes; a receiver configured to receive a signal including synchronization information of a frame; a distributor configured to divide data included in the received signal into frame elements and cause the plurality of logical lanes to store the data; and a transmitter configured to transmit the data stored in the logical lanes to lines corresponding to the logical lanes. When the data is stored in the plurality of logical lanes, the distributor groups the logical lanes into a plurality of groups and associates the frame elements with the synchronization information. | 05-14-2015 |