Patent application number | Description | Published |
20100072614 | 3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD - A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer. | 03-25-2010 |
20110216573 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter. | 09-08-2011 |
20110309881 | THREE-DIMENSIONAL SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor. | 12-22-2011 |
20120235705 | NONVOLATILE CONFIGURATION MEMORY - According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer. | 09-20-2012 |
20130268795 | CACHE SYSTEM AND INFORMATION-PROCESSING DEVICE - According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit. | 10-10-2013 |
20130322161 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential. | 12-05-2013 |
20140104920 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps. | 04-17-2014 |
20140281189 | PROCESSOR SYSTEM HAVING VARIABLE CAPACITY MEMORY - According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2 | 09-18-2014 |
20140297920 | MULTI-CORE PROCESSOR AND CONTROL METHOD - According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer. | 10-02-2014 |
20140379975 | PROCESSOR - According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas. | 12-25-2014 |
Patent application number | Description | Published |
20090302394 | CMOS INTEGRATED CIRCUITS WITH BONDED LAYERS CONTAINING FUNCTIONAL ELECTRONIC DEVICES - A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices. | 12-10-2009 |
20090309646 | RANDOM NUMBER GENERATION DEVICE - A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film. | 12-17-2009 |
20090327379 | RANDOM NUMBER GENERATING DEVICE - A random number generating device includes: a pulse voltage generator configured to generate a pulse voltage having an amplitude of 26 mV or more; a random noise generating element including source and drain regions formed at a distance from each other on a semiconductor substrate, a tunnel insulating film formed on a portion of the semiconductor substrate located between the source region and the drain region, and a gate electrode formed above the tunnel insulating film and to which the pulse voltage is applied, the random noise generating element configured to generate a random noise contained in a current flowing between the source region and the drain region; and a random number generating unit configured to generate a random number signal based on the random noise. | 12-31-2009 |
20110205780 | Semiconductor Integrated Circuit - In one embodiment, a semiconductor integrated circuit includes a first resistive-change element, a second resistive-change element and a first switching element. The first resistive-change element includes one end having a first polarity connected to a first power source. The first resistive-change element includes another end having a second polarity connected to an output node. The second resistive-change element includes one end having the second polarity connected to the output node. The first switching element includes a first terminal connected to another end of the second resistive-change element. The first switching element includes a second terminal connected to a second power source. | 08-25-2011 |
20120080737 | SEMICONDUCTOR DEVICE PROVIDED WITH A NON-VOLATILE MEMORY UNIT AND A MEMS SWITCH - According to one embodiment, a semiconductor device is provided. The semiconductor is provided with a MEMS switch element having a control terminal and a pair of signal terminals, and a non-volatile memory unit having first and second non-volatile semiconductor elements. The first non-volatile semiconductor element has a first source, a first drain and a first control gate terminal. The first drain is electrically connected to the control terminal of the MEMS switch element. The second non-volatile semiconductor element has a second source, a second drain and a second control gate terminal. The second drain gate terminal is electrically connected to the control terminal of the MEMS switch element. | 04-05-2012 |
20120089656 | RANDOM NUMBER GENERATOR CIRCUIT AND CRYPTOGRAPHIC CIRCUIT - A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection. | 04-12-2012 |
20120168290 | SWITCH DEVICE AND CIRCUIT INCLUDING SWITCH DEVICE - According to one embodiment, a switch device includes a first switching unit provided on a base substance. The first switching unit includes a first supporting electrode, a first beam, a first contact point electrode, a first floating conductive layer and a first control electrode. The first supporting electrode is fixed to the base. The first beam includes a first holding part and a first movable part. The first holding part is fixed to the base. The first movable part has one end connected to the first holding part. The first contact point electrode is fixed to the base and faces the first movable part. The first floating conductive layer is fixed to the first movable part via a first insulating part and stores a charge. The first control electrode is fixed to the base and faces the first floating conductive layer. | 07-05-2012 |
20120223440 | METHOD OF MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT APPARATUS - In a three-dimensional integrated circuit apparatus | 09-06-2012 |
20120230105 | Semiconductor Integrated Circuit - In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted. | 09-13-2012 |
20120233377 | Cache System and Processing Apparatus - According to an embodiment, a cache system includes a volatile cache memory, a nonvolatile cache memory, an address decoder, and an evacuation unit. The nonvolatile cache memory has a capacity equal to the volatile cache memory. The address decoder designates a same line to the volatile cache memory and the nonvolatile cache memory. The evacuation unit stores data which is inputted from the volatile cache memory and outputs the stored data to the volatile cache memory. | 09-13-2012 |
20120243336 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor. | 09-27-2012 |
20120246412 | CACHE SYSTEM AND PROCESSING APPARATUS - According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory. | 09-27-2012 |
20120250399 | MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal. | 10-04-2012 |
20130027093 | PLL - One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value. | 01-31-2013 |
20130028012 | SEMICONDUCTOR INTEGRATED CIRCUIT AND PROCESSOR - In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal. | 01-31-2013 |
20130031397 | INFORMATION PROCESSING APPARATUS - One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register. | 01-31-2013 |
20130055189 | METHOD FOR IMPLEMENTING CIRCUIT DESIGN FOR INTEGRATED CIRCUIT AND COMPUTER READABLE MEDIUM - In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length. | 02-28-2013 |
20130069134 | MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES - In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region. | 03-21-2013 |
20130246818 | CACHE DEVICE, CACHE SYSTEM AND CONTROL METHOD - According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed. | 09-19-2013 |
20130257477 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories. | 10-03-2013 |
20130307054 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories. | 11-21-2013 |
20140293685 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a plurality of memory cells, each memory cell including a first MTJ element and a first selection unit; a pair of a first and second bit lines provided to each column of the memory cells; a word line provided to each row of the memory cells; an equalizer circuit provided to each column of the memory cells, and to connect between the first and second bit lines; and a control circuit that sets the first and second bit lines connected to a selected memory cell to be a first and second potentials to conduct a write operation, and after the write operation, transmits a control signal to the equalizer circuit between the first and second bit lines to activate the equalizer circuit to equalize potentials of the first bit line and the second bit line, thereby bringing into floating states. | 10-02-2014 |
20140332895 | RANDOM NUMBER GENERATION DEVICE - A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film. | 11-13-2014 |
20140339616 | NON-VOLATILE MEMORY, WRITING METHOD FOR THE SAME, AND READING METHOD FOR THE SAME - A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node. | 11-20-2014 |