Patent application number | Description | Published |
20080231351 | VOLTAGE STEP-DOWN CIRCUIT - According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state. | 09-25-2008 |
20090116273 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a memory including: unit cells having ferroelectric capacitors and cell transistors; two depletion transistors and two enhancement transistors serially connected between two adjacent unit series configurations configured by serially connecting the unit cells; four selective lines respectively connected to the gates of the two enhancement transistors and the two depletion transistors; word lines connected to the gates of the cell transistors; a bit line connected to the unit series configuration via at least one of the enhancement transistors and the depletion transistors; and a bit line contact connecting the bit line to at least one of the enhancement transistors and the depletion transistors, wherein in two of adjacent bit lines, the bit line contact connected to one of the two adjacent bit lines and the bit line contact connected to the other bit line are opposed to each other with respect to one of the selective lines. | 05-07-2009 |
20090256542 | POWER SUPPLY CIRCUIT - A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage. | 10-15-2009 |
20090282318 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the present invention includes a memory cell array that includes a ferroelectric capacitor and a selection transistor that selects a column of the memory cell array and connects the selected column to a bit line. A plate line applies a potential for reading or writing data to the ferroelectric capacitor. A sense amplifier circuit compares and amplifies a signal read from the ferroelectric capacitor to the bit line. A plate line control circuit controls a potential of the plate line synchronously with a clock signal. | 11-12-2009 |
20090323390 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line. | 12-31-2009 |
20100014342 | SEMICONDUCTOR STORAGE DEVICE - A memory includes a cell block comprises memory cells connected in series; block select transistors connected to one ends of the cell blocks; bit lines; plate lines; a sense amplifier comprises an N-type sensor and a P-type sensor, the N-type sensor applying a low-level potential to the bit line, and the P-type sensor applying a high-level potential to the bit line; local data lines corresponding to the bit lines respectively and transmitting data; and a column select transistor between one of the bit lines and one of the local data lines; wherein either one of the P-type sensor and the N-type sensor is set in an inactive state with the other one of the P-type sensor and the N-type sensor being in an active state, when the column select transistor is turned on to transmit the data to be written from the local data line to the bit line. | 01-21-2010 |
20100118586 | FERROELECTRIC MEMORY - A ferroelectric memory of an embodiment of the present invention includes a plurality of units, in each of which a ferroelectric capacitor and a transistor are connected to each other in parallel. The memory includes first and second memory cell arrays, first and second bit lines arranged in the first and second memory cell arrays, respectively, first and second blocks connected to the first bit line, and including N | 05-13-2010 |
20110249485 | RESISTANCE-CHANGE MEMORY - According to one embodiment, a resistance-change memory includes bit lines running in a first direction, word lines running in a second direction, and a memory cell array includes memory cells each includes a selection transistor and a variable resistance element. In a layout of first to fourth variable resistance elements arranged in order in the first direction, the first variable resistance element and the second variable resistance element sandwich one word line therebetween, the third variable resistance element and the fourth variable resistance element sandwich one word line therebetween, a first pair includes the first and second variable resistance elements and a second pair includes the third and fourth variable resistance elements sandwich two word lines therebetween, and a column is constructed by repeating the layout in the first direction. | 10-13-2011 |
20150055403 | MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR - According to one embodiment, a memory device includes: a nonvolatile memory that stores data according to a write access; an address memory that stores a first address described with a gray code; a first counter that counts up the first address for each write access, generates a second address as the count-up result, and supplies the second address to the nonvolatile memory; a rounding circuit configured to calculate a third address that is equal to or larger than a final output of the first counter and larger than the first address by one or a power of two after a series of write accesses is completed; and a controller that rewrites the third address in the address memory. | 02-26-2015 |