Patent application number | Description | Published |
20110153649 | AUTOMATIC SEARCH AND TRANSFER APPARATUS AND AUTOMATIC SEARCH AND TRANSFER SYSTEM - It is an object of the present invention to provide an automatic search and transfer apparatus, in which a condition for finding data that is desired is specified beforehand, and that continuously monitor data created in network-connected computers, automatically collect data that matches the condition, and put the data into a usable state. Herein discloses is an automatic search and transfer apparatus that automatically searches for and transfers data from a computer connected via a network. The apparatus comprising: a keyword input section that inputs a keyword; a search section that searches for data including the keyword and acquires attribute data of concerned data from the computer connected via the network; a reporting section that reports information relating to the concerned data; a reception section that receives the concerned data; and a data storage section that stores the data. The reporting section reports acquisition of the attribute data of the concerned data when the attribute data is acquired, and the reception section starts reception of the concerned data after the reporting section has reported the acquisition of the attribute data of the concerned data. | 06-23-2011 |
20120075910 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a semiconductor integrated circuit includes first and second resistance change type memory element and first and second switches. The first resistance change type memory element includes a first terminal connected to a first power supply and a second terminal connected to a first node. The second resistance change type memory element includes a third terminal connected to the first node and a fourth terminal connected to a second power supply. The first switch includes one end of a first current path connected to a first program power supply and the other end of the first current path connected to the first node. The second switch includes one end of a second current path connected to the first node and the other end of the second current path connected to a second program power supply. | 03-29-2012 |
20120230105 | Semiconductor Integrated Circuit - In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted. | 09-13-2012 |
20120235705 | NONVOLATILE CONFIGURATION MEMORY - According to one embodiment, a memory includes a first P-channel FET having a gate connected to a second output node, a source applied to a first potential, and a drain connected to the first output node, a second P-channel FET having a gate connected to a first output node, a source applied to the first potential, and a drain connected to the second output node, a first N-channel FET having a control gate connected to a first word line, a source applied to a second potential lower than the first potential, a drain connected to the first output node, and a threshold changed by data in a storage layer, and a second N-channel FET having a control gate connected to a second word line, a source applied to the second potential, a drain connected to the second output node, and a threshold changed by data in a storage layer. | 09-20-2012 |
20120243336 | NONVOLATILE PROGRAMMABLE LOGIC SWITCH - An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor. | 09-27-2012 |
20130027093 | PLL - One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value. | 01-31-2013 |
20130055189 | METHOD FOR IMPLEMENTING CIRCUIT DESIGN FOR INTEGRATED CIRCUIT AND COMPUTER READABLE MEDIUM - In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length. | 02-28-2013 |
20130215670 | MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY - A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state. | 08-22-2013 |
20130222011 | PROGRAMMABLE LOGIC SWITCH - One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. | 08-29-2013 |
20130235688 | LOOK-UP TABLE CIRCUIT - One embodiment provides a look-up table circuit, including: 2 | 09-12-2013 |
20130248959 | PROGRAMMABLE LOGIC SWITCH - According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. | 09-26-2013 |
20130257477 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a first input wire; a second input wire; a first look-up table (LUT) comprising: a plurality of first memories; a first number of first switches connected to the first input wire; and a second number of second switches connected to the second input wire, the second number being less than the first number, the first LUT being configured to output information which is stored in one of the first memories; and a second LUT including: a plurality of second memories; a third number of third switches connected to the second input wire; and a fourth number of fourth switches connected to the first input wire, the fourth number being less than the third number, the second LUT being configured to output information which is stored in one of the second memories. | 10-03-2013 |
20130258782 | CONFIGURATION MEMORY - According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node. | 10-03-2013 |
20130307054 | SEMICONDUCTOR INTEGRATED CIRCUIT - One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories. | 11-21-2013 |
20140022840 | NON-VOLATILE PROGRAMMABLE SWITCH - According to one embodiment, a non-volatile programmable switch according to this embodiment includes first and second non-volatile memory transistors, and a common node that is connected to the output side terminals of the first and second non-volatile memory transistors, and a logic transistor unit that is connected to the common node. A length of a gate electrode of the first and second non-volatile memory transistors in a channel longitudinal direction is shorter than a length of the charge storage film in the channel longitudinal direction. | 01-23-2014 |
20140035616 | RECONFIGURABLE INTEGRATED CIRCUIT DEVICE AND WRITING METHOD THEREOF - A reconfigurable integrated circuit device includes a memory unit for storing configuration information. The memory unit has a nonvolatile memory transistor having a gate connected to a first wire, a first terminal connected to a second wire, and a second terminal connected to a third wire. The memory unit also includes a switch circuit connected to the third wire. The switch circuit alters the configuration of the integrated circuit device by, for example, opening and closing to make wiring connections or disconnections. The integrated circuit device additionally includes a data supply circuit for supplying bit data and a first power supply circuit for supplying voltages to the first wire for storing bit data in the first nonvolatile memory transistor and for storing bit data as a charge level on the third wire. | 02-06-2014 |
20140035618 | CIRCUIT HAVING PROGRAMMABLE MATCH DETERMINATION FUNCTION, AND LUT CIRCUIT, MUX CIRCUIT AND FPGA DEVICE WITH SUCH FUNCTION AND METHOD OF DATA WRITING - A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line. | 02-06-2014 |
20140131811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a first transistor having a first source region and a first drain region arranged in a first protruded semiconductor region, a first channel region having a first corner portion in its upper portion in a section perpendicular to a first direction, the first corner portion having a first radius of curvature; a second transistor having a second source region and a second drain region arranged in a second protruded semiconductor region, and a second channel region having a second corner portion in its upper portion in a section that is perpendicular to a second direction, the second corner portion having a second radius of curvature greater than the first radius of curvature. | 05-15-2014 |
20140143292 | RANDOM NUMBER GENERATING CIRCUIT - According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency. | 05-22-2014 |
20140372671 | AUTHENTICATION DEVICE, AUTHENTICATION METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit. | 12-18-2014 |