Patent application number | Description | Published |
20080229026 | System and method for concurrently checking availability of data in extending memories - This invention discloses an extended memory comprising a first tag RAM for storing one or more tags corresponding to data stored in a first storage module, and a second tag RAM for storing one or more tags corresponding to data stored in a second storage module, wherein the first and second storage modules are separated and independent memory units, the numbers of bits in the first and second tag RAMs differ, and an address is concurrently checked against both the first and second tag RAMs using a first predetermined bit field of the address for checking against a first tag from the first tag RAM and using a second predetermined bit field of the address for checking against a second tag from the second tag RAM. | 09-18-2008 |
20090002058 | Automatic Bias Circuit for Sense Amplifier - The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory. | 01-01-2009 |
20090141573 | System and Method for Better Testability of OTP Memory - A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory. | 06-04-2009 |
20100329061 | ELECTRICAL FUSE CIRCUIT FOR SECURITY APPLICATIONS - A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation. | 12-30-2010 |
Patent application number | Description | Published |
20080224785 | Temperature tracking oscillator circuit - A temperature-dependent oscillator includes a first current source, wherein a first current provided by the first current source has a positive temperature coefficient, a second current source serially connected to the first current source, wherein a second current provided by the second current source has a negative temperature coefficient, and a capacitor serially connected to the first current source and parallel connected to the second current source. | 09-18-2008 |
20090086530 | System and method for reading multiple magnetic tunnel junctions with a single select transistor - A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs. | 04-02-2009 |
20090166872 | Memory Word lines with Interlaced Metal Layers - A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance. | 07-02-2009 |
20090194829 | MEMS Packaging Including Integrated Circuit Dies - MEMS packaging schemes having a system-on-package (SOP) configuration and a system-on-board (SOB) configuration are provided. The MEMS package comprises one or more MEMS dies, a cap section having one or more integrated circuit (IC) dies, and a packaging substrate or a printed circuit board (PCB) arranged in a stacking manner. Vertical connectors, such as through-silicon-vias (TSVs), are formed to provide short electrical connections between the various components. The MEMS packaging schemes enable higher integration density, reduced MEMS package footprints, reduced RC delays and power consumption. | 08-06-2009 |
20090251975 | Circuit and Method for a Sense Amplifier with Instantaneous Pull Up/Pull Down Sensing - A circuit and method for a sense amplifier for sensing the charge stored when a select signal couples a memory cell to the sense amplifier. A pull up voltage and a pull down voltage are instantaneously supplied to the sense amplifier to sense the small signal differential input on the complementary bit lines and to simultaneously restore the value stored in the memory cell. A differential output signal generator circuit is provided to instantaneously supply the pull up and pull down voltages. In another preferred embodiment the signal generator provides the pull up and pull down voltages at a first level and subsequently increases the pull up voltage to a voltage greater than the positive supply voltage and decreases the pull down voltage. A method of sensing is disclosed wherein the sense and restore actions are performed instantaneously to provide memory cell sensing with greater tolerance of device mismatches. | 10-08-2009 |
20090294798 | Bipolar Device Compatible with CMOS Process Technology - A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device. | 12-03-2009 |
20100026601 | Antennas Integrated in Semiconductor Chips - An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring. | 02-04-2010 |
20100123483 | Circuit and Method for a Digital Process Monitor - A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed. | 05-20-2010 |
Patent application number | Description | Published |
20080217734 | Multi-level electrical fuse using one programming device - A multi-level electrical fuse system comprises at least one fuse box having at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels. | 09-11-2008 |
20080238739 | SYSTEM AND METHOD FOR CALIBRATING DIGITAL-TO-ANALOG CONVERTORS - A system and method for calibrating a digital-to-analog converter (DAC) is disclosed, the method comprises providing a plurality of spare bits to each of a group of DAC bits that are designated for calibration, calibrating a first DAC bit of the group of DAC bits using its corresponding plurality of spare bits, and keeping a second DAC bit of the group of DAC bits unchanged while calibrating the first DAC bit. | 10-02-2008 |
20080238744 | DIGITAL-TO-ANALOG CONVERTER CELL - A DAC cell comprising: two or more PMOS core devices coupled in series between a power supply and a steering node; a first core transistor coupled between the steering node and a complementary power supply line and controlled by a control signal; and a second core transistor coupled between the steering node and an output of the DAC cell and controlled by a logical inverse of the control signal, wherein the control signal and its logical inverse direct a current from the steering node to either the complementary power supply line or to the output of the DAC cell based on the control signal. | 10-02-2008 |
20080251884 | Method and System for Controlling Multiple Electrical Fuses with One Program Device - A fuse circuit comprising one or more one-time programmable electrical fuses; one or more unidirectional conductive devices each coupled to one of the fuses; a programming device coupled to the unidirectional conductive devices; and a selection module coupled to the electrical fuses for selecting a predetermined electrical fuse, wherein upon a selection by the selection module, a programming current is introduced through at least one selected electrical fuse, wherein the selection module is an N-to-one multiplexer selecting one of the N number of electrical fuses to be programmed, and the unidirectional conductive devices not coupled to the selected electrical fuse to prevent the programming current from interfering with the remaining electrical fuses. | 10-16-2008 |
20080258255 | Electromigration Aggravated Electrical Fuse Structure - A fuse structure with aggravated electromigration effect is disclosed, which comprises an anode area overlaying a first plurality of contacts that are coupled to a positively high voltage during a programming of the fuse structure, a cathode area overlaying a second plurality of contacts that are coupled to a complementary low voltage during a programming of the fuse structure, and a fuse link area having a first and second end, wherein the first end contacts the anode area at a predetermined distance to the nearest of the first plurality of contacts, and the second end contacts the cathode area at the predetermined distance to the nearest of the second plurality of contacts, wherein the cathode area is smaller than the anode area for the aggravating electromigration effect. | 10-23-2008 |
20100020590 | SRAM WITH IMPROVED READ/WRITE STABILITY - A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation. | 01-28-2010 |
20120243290 | MULTI-LEVEL ELECTRICAL FUSE USING ONE PROGRAMMING DEVICE - A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels. | 09-27-2012 |