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Shinagawa, Tokyo
Junichi Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100175907 | POLYMER BUSHING AND CABLE TERMINATION USING THE SAME - A polymer bushing includes a conductor bar, a conductor insertion hole at a lower end, a rigid insulator around the outer circumference of the conductor bar and having a receiving port for a cable termination, a polymer covering around | 07-15-2010 |
Katsutoshi Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100126841 | Dome sheet unit and membrane switch having the same - A membrane switch can attach an elastically deformable dome to a board in a reliable manner such that the dome is not detached even if a fixing sheet is made thinner and smaller and therefore has a smaller footprint. This switch has: a dome ( | 05-27-2010 |
Kazuhiko Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20110107739 | WARM-UP METHOD AND SYSTEM FOR WARMING UP EXHAUST PURIFICATION CATALYST - A warm-up system for warming up an exhaust purification catalyst arranged in an exhaust passage of an engine equipped with a turbocharger. The warm-up system includes an electric motor coupled to a turbine of the turbocharger, and control device that operates the electric motor to apply counter torque to the turbine when the exhaust purification catalyst needs to be warmed up. | 05-12-2011 |
| 20110146274 | METHOD AND SYSTEM FOR REGENERATING PARTICULATE FILTER - A particulate filter regeneration system regenerates a particulate filter provided in an exhaust line of an engine equipped with a turbocharger by burning matter trapped on the particulate filter by raising the temperature of exhaust gas at times that the particulate filter requires regeneration. The system has an electric motor functioning as an intake quantity regeneration portion capable of increasing the flow rate of compressed air without depending on the flow rate of exhaust gas flowing across a turbine of the turbocharger, a bypass line connecting an engine intake line upstream of the engine to a section of the exhaust line upstream of the particulate filter, a flow rate regulation valve regulating the flow rate in the bypass line, and a control portion controlling the electric motor and the flow rate regulator. | 06-23-2011 |
Masashi Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080270868 | DECODING APPARATUS - In the present application, there is provided a decoding apparatus for decoding low density parity check codes, including: a plurality of storage sections configured to store logarithmic likelihood ratios or logarithmic posteriori probability ratios for one codeword into addresses thereof which are independent of each other thereamong; and a readout section configured to simultaneously read out, from among the logarithmic likelihood ratios or logarithmic posteriori probability ratios for the one codeword stored in the storage sections, a plurality of ones of the logarithmic likelihood ratios or logarithmic posteriori probability ratios which correspond to non-zero value elements in a predetermined one row of the check matrix used in a coding process of the low density parity check codes. | 10-30-2008 |
| 20080320370 | CRC generator polynomial select method, CRC coding method and CRC coding circuit - Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding processing and/or CRC processing of inspecting a CRC processing result, the CRC generator polynomial select method may include a first process of finding largest minimum Hamming distances Max.d | 12-25-2008 |
| 20100031124 | Transmission apparatus and method, reception apparatus and method, and program - A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing. | 02-04-2010 |
| 20100229076 | Decoding Apparatus and Decoding Method - Disclosed herein is a decoding apparatus including: with N and x each being a positive integer and k being a positive integer being equal to or greater than 1, a shift register of k stages configured to accumulate path select information for k inputs that is information about a survivor path of xN bits made up of radix-2 | 09-09-2010 |
| 20110029838 | Device and Method for Transmission, Device and Method for Reception, and Program - The present invention relates to a device and a method for transmission, a device and a method for reception, and a program that make it possible to obtain an undetected error probability characteristic close to a limit value in a system using a CRC for a plurality of pieces of data having different code lengths. A generator polynomial for header data which generator polynomial is used when a CRC coding process is performed on header data and a generator polynomial for sub-header data which generator polynomial is used when the CRC coding process is performed on sub-header data are set in a transmitting device | 02-03-2011 |
Miki Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20110079120 | LONG SHAFT INNER SURFACE MACHINING APPARATUS AND METHOD THEREFOR - A long shaft inner surface machining apparatus of the present invention includes: a long shaft support device | 04-07-2011 |
Mitsuru Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080205904 | Electric Field Sensor Device, Transceiver, Positional Information Obtaining System, and Information Input System - When a human hand ( | 08-28-2008 |
Taishi Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090210553 | Packet forwarding apparatus using token bucket algorithm and leaky bucket algorithm - A packet forwarding apparatus and network system for providing different types of bandwidth control services to the user; in which a packet forwarding apparatus for transferring data comprises an interface unit for sending and receiving packets, and a traffic shaper for controlling the packet transmission timing and a packet switch for sending an output to the interface unit as the destination of the received packet; and the traffic shaper uses a token bucket algorithm when transmitting a packet to guarantee the minimum frame rate, and uses a leaky bucket algorithm when limiting the peak frame rate. | 08-20-2009 |
| 20100080558 | Passive Optical Network System and Operating Method Thereof - The passive optical network includes a master station and slave stations connected via an optical fiber network including an optical splitter and a plurality of optical fibers. The master station includes a bandwidth control unit which decides a volume of a transmission signal to be granted to each slave station in every first period and in accordance with a request from the slave station, and a transmission timing control unit which decides, in one of a plurality of second periods and in accordance with the decided volume of the signal, transmission timing in which the slave station should transmit a signal. When the signal is to be transmitted by division over the plurality of second periods, the bandwidth control unit or the transmission timing control unit is controlled based on a volume of a signal to be attached by division processing, so that the granted signal can be transmitted in the first period. | 04-01-2010 |
Tatsuyuki Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100051939 | NITRIDE BASED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An interfacial reaction suppressing layer | 03-04-2010 |
| 20100283083 | Normally-off field effect transistor using III-nitride semiconductor and method for manufacturing such transistor - Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region. | 11-11-2010 |
Yoshihisa Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100113660 | RESIN COMPOSITION - To provide a resin composition comprising an aromatic polycarbonate resin and having excellent appearance, impact strength, thermal stability, hydrolysis resistance, and flame retardancy. | 05-06-2010 |
Yutaka Shinagawa, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090052238 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more. | 02-26-2009 |
| 20100220531 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 09-02-2010 |