Patent application number | Description | Published |
20110210320 | ANTHRACENE DERIVATIVE AND ORGANIC ELECTROLUMINESCENCE ELEMENT USING THE SAME - The present invention relates to an anthracene derivative and an organic electroluminescent device using the same. More specifically, the present invention relates to: a novel compound which has a core (for example, an indenoanthracene core) where both an anthracene moiety with excellent device characteristics and a fluorene moiety with excellent fluorescent properties are fused, wherein substituents (for example, a heterocyclic group such as a benzimidazole group, a benzothiazole group, a benzoxazole group, a pyridinyl group or a bipyridinyl group) with an electron transfer capacity are substituted to the core; and an organic electroluminescence element which has improved luminous efficiency, brightness, thermal stability, driving voltage, and lifetime, by comprising an organic layer which is positioned between a positive electrode and negative electrode and contains the novel compound. | 09-01-2011 |
20130009136 | TRIPHENYLENE-BASED COMPOUNDS AND ORGANIC ELECTROLUMINESCENT DEVICE COMPRISING SAME - The present invention relates to a triphenylene-based compound represented by the following Formula 1 and an organic electroluminescent device including the same, and the compound of the present invention has excellent hole injection and/or transporting ability, electron transporting ability, and/or light emitting ability, and particularly, green and red light emitting ability, and thus in an organic electroluminescent device containing the same as a light emitting host material, characteristics such as luminous efficiency, luminance, thermal stability, driving voltage, service life and the like may be improved. | 01-10-2013 |
Patent application number | Description | Published |
20110195308 | Secondary particle and lithium battery including secondary particle - A secondary particle and a lithium battery including the same are provided wherein the secondary particle includes a plurality of primary particles and each primary particle contains n polycyclic nano-sheets disposed upon one another. The polycyclic nano-sheets include hexagonal rings of six carbon atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L | 08-11-2011 |
20110274970 | NEGATIVE ACTIVE MATERIAL AND LITHIUM BATTERY - A negative active material containing super-conductive nanoparticles coated with a high capacity negative material and a lithium battery including the same are provided, wherein the super-conductive nanoparticles have a structure in which polycyclic nano-sheets are stacked upon one another along a direction perpendicular to a first plane. The polycyclic nano-sheets include hexagonal rings of six carbons atoms linked to each other, wherein a first carbon and a second carbon have a distance therebetween of L | 11-10-2011 |
20120270108 | ANODE ACTIVE MATERIAL, ANODE AND LITHIUM BATTERY INCLUDING THE MATERIAL, AND METHOD OF PREPARING THE MATERIAL - In one aspect, an anode active material is provided. The anode active material may include a crystalline carbon-based material that includes a core having a lattice spacing d | 10-25-2012 |
20120288766 | NEGATIVE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND LITHIUM BATTERY INCLUDING THE SAME - Provided are a negative active material, a method of preparing the same, and a lithium battery including the negative active material. The negative active material includes a carbonaceous core that has a sulfur content of about 10 ppm to 900 ppm; and an amorphous carbon layer continuously formed on a surface of the carbonaceous core, wherein the carbonaceous core has a crystalloid plate structure, and a crystallite size measured from a full width at half maximum of the peak with respect to the surface (002) of about 10 nm to about 45 nm in an X-ray diffraction spectrum of the carbonaceous core. The lithium battery including a negative electrode including the negative active material has improved capacity characteristics and ring lifetime characteristics. | 11-15-2012 |
20120288768 | NEGATIVE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND LITHIUM BATTERY INCLUDING THE SAME - Provided are a negative active material, a method of preparing the same, and a lithium battery including the negative active material, wherein the negative active material includes a carbonaceous material that has a peak with respect to a surface (002) at a Bragg angle 2θ of 26.4°±0.1° in an X-ray diffraction spectrum, has a full width at half maximum of the peak with respect to the surface (002) of about 0.2° to about 0.6°, has an interlayer spacing (d | 11-15-2012 |
20130004846 | NEGATIVE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND LITHUM BATTERY INCLUDING NEGATIVE ACTIVE MATERIAL - A negative active material, a method of preparing the same, and a lithium battery including the negative active material are disclosed. The negative active material includes a silicon-based nanocore and a first amorphous carbonaceous coating layer that is formed of carbonized organic material and that is uniformly and continuously formed on a surface of the silicon-based nanocore, whereby irreversible capacity losses due to volumetric expansion/contraction caused when a lithium battery is charged and discharged are compensated and cycle lifetime characteristics are enhanced. | 01-03-2013 |
20130089783 | Negative Active Material and Lithium Battery Containing the Negative Active Material - A negative active material and a lithium battery including the same are disclosed. Due to the inclusion of silicon nanowires formed on a spherical carbonaceous base material, the negative active material may increase the capacity and cycle lifespan characteristics of the lithium battery. | 04-11-2013 |
20130089784 | NEGATIVE ACTIVE MATERIAL AND LITHIUM BATTERY CONTAINING THE NEGATIVE ACTIVE MATERIAL - A negative active material and a lithium battery including the negative active material. The negative active material includes primary particles, each including: a crystalline carbonaceous core having a surface on which silicon-based nanowires are disposed; and an amorphous carbonaceous coating layer that is coated on the crystalline carbonaceous core so as not to expose at least a portion of the silicon-based nanowires. Due to the inclusion of the primary particles, an expansion ratio is controlled and conductivity is provided and thus, a formed lithium battery including the negative active material may have improved charge-discharge efficiency and cycle lifespan characteristics. | 04-11-2013 |
20130209881 | NEGATIVE ACTIVE MATERIAL AND LITHIUM BATTERY INCLUDING NEGATIVE ACTIVE MATERIAL - A negative active material and a lithium battery including the negative active material. The negative active material includes a non-carbonaceous nanoparticle capable of doping or undoping lithium; and a crystalline carbonaceous nano-sheet, wherein at least one of the non-carbonaceous nanoparticle and the crystalline carbonaceous nano-sheet includes a first amorphous carbonaceous coating layer on its surface, and thus an electrical conductivity thereof is improved. In addition, a lithium battery including the negative active material has an improved efficiency and lifetime. | 08-15-2013 |
20140045060 | COMPOSITE ANODE ACTIVE MATERIAL, ANODE AND LITHIUM BATTERY EACH INCLUDING THE COMPOSITE ANODE ACTIVE MATERIAL, AND METHOD OF PREPARING THE COMPOSITE ANODE ACTIVE MATERIAL - In an aspect, a composite anode active material including a composite core; and a coating layer covering at least a region of the composite core, wherein the composite core comprises a carbonaceous substrate; and a nanostructure disposed on the substrate, and the coating layer includes a metal oxide; an anode and a lithium battery each including the composite anode active material; and a method of preparing the composite anode active material are provided. | 02-13-2014 |
20140050984 | COMPOSITE ANODE ACTIVE MATERIAL, ANODE AND LITHIUM BATTERY COMPRISING THE MATERIAL, AND METHOD OF PREPARING THE SAME - A composite anode active material, an anode and a lithium battery each including the composite anode active material, and a method of preparing the composite anode active material. The composite anode active material includes a composite core, and a coating layer covering at least a region of the composite core, wherein the composite core includes a carbonaceous substrate and a metal/semi-metal nanostructure on the carbonaceous substrate, the coating layer is more predominant on the nanostructure than on the carbonaceous substrate, and the coating layer includes a metal oxide. | 02-20-2014 |
20140079991 | LITHIUM BATTERY - Provided is a lithium battery including: a positive electrode, a negative electrode, and an organic electrolytic solution, wherein the negative electrode has a metal/metalloid nanostructure, and the organic electrolytic solution includes a lithium sulfonimide-based compound. | 03-20-2014 |
20140147741 | COMPOSITE ANODE ACTIVE MATERIAL, ANODE AND LITHIUM BATTERY CONTAINING THE SAME, AND METHOD OF PREPARING THE COMPOSITE ANODE ACTIVE MATERIAL - In an aspect, a composite anode active material including: a porous particles, said porous particles including: a plurality of composite nanostructures; and a first carbonaceous material binding the composite nanostructures, wherein the porous particles have pores within the particle, and wherein the composite nanostructures include a crystalline second carbonaceous material substrate including at least one carbon nano-sheet, and a plurality of metal nanowires arranged at intervals on the crystalline second carbonaceous material substrate is disclosed. | 05-29-2014 |
20140234710 | NEGATIVE ACTIVE MATERIAL, NEGATIVE ELECTRODE, AND LITHIUM BATTERY - A negative active material includes a conductive unit bound in island-like form to silicon-based nanowires on a carbonaceous base. Such negative active material may improve the electrical conductivity of the silicon-based nanowires, and suppress separation of the silicon-based nanowires caused from volume expansion, and thus may improve lifetime characteristics of a lithium battery. | 08-21-2014 |
20140234714 | NEGATIVE ACTIVE MATERIAL, AND NEGATIVE ELECTRODE AND LITHIUM BATTERY EACH INCLUDING THE NEGATIVE ACTIVE MATERIAL - A negative active material and a lithium battery are provided. The negative active material includes a composite core, and a coating layer formed on at least part of the composite core. The composite core includes a carbonaceous base and a metal/metalloid nanostructure disposed on the carbonaceous base. The coating layer includes a metal oxide coating layer and an amorphous carbonaceous coating layer. | 08-21-2014 |
20150072233 | NEGATIVE ACTIVE MATERIAL AND LITHIUM BATTERY CONTAINING THE NEGATIVE ACTIVE MATERIAL - A negative active material and a lithium battery including the same are disclosed. The negative active material includes a primary particle including a silicon nanowire formed on a non-carbonaceous conductive core to increase the capacity and cycle lifespan properties of the lithium battery. | 03-12-2015 |
Patent application number | Description | Published |
20110244666 | Methods Of Manufacturing Stair-Type Structures And Methods Of Manufacturing Nonvolatile Memory Devices Using The Same - Methods of manufacturing stair-type structures and methods of manufacturing nonvolatile memory devices using the same. Methods of manufacturing stair-type structures may include forming a plurality of thin layers stacked in plate shapes, forming a mask on an utmost thin layer, patterning the utmost layer using the mask as an etch mask, escalating a width of the mask and etching each of the thin layers at a different width of the mask to form a stair-type structure of the thin layers. Control gates may be formed into the stair-type structures using the methods of manufacturing stair-type structures. | 10-06-2011 |
20130056823 | SEMICONDUCTOR DEVICES - A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures. | 03-07-2013 |
20130095433 | PHOTOLITHOGRAPHY METHOD INCLUDING DUAL DEVELOPMENT PROCESS - A photolithography method includes coating a photoresist on an active region and an edge region of a wafer, exposing the photoresist on the edge region to first ultraviolet rays, exposing the photoresist on the active region to second ultraviolet rays, depositing a first developing solution on the photoresist on the edge region to remove the photoresist on the edge region, and developing the photoresist on the active region using a second developing solution. | 04-18-2013 |
20130178067 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns. | 07-11-2013 |
20140370712 | METHODS OF FORMING A PATTERN AND DEVICES FORMED BY THE SAME - The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced. | 12-18-2014 |
Patent application number | Description | Published |
20110220964 | SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 09-15-2011 |
20110241071 | Semiconductor Devices Having Field Effect Transistors With Epitaxial Patterns in Recessed Regions - A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region. | 10-06-2011 |
20120241815 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 09-27-2012 |
20120244674 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip. | 09-27-2012 |
20120302018 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 11-29-2012 |
20130089961 | Methods of Forming Semiconductor Devices Including an Epitaxial Layer and Semiconductor Devices Formed Thereby - Methods of forming a semiconductor device are provided. The methods may include forming an epitaxial layer by growing a crystalline layer using a semiconductor source gas in a reaction chamber, and by etching the crystalline layer using an etching gas in the reaction chamber. | 04-11-2013 |
20130109144 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME | 05-02-2013 |
20140084350 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface. | 03-27-2014 |
20140087535 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region. | 03-27-2014 |
20140087537 | SEMICONDUCTOR DEVICES INCLUDING MULTILAYER SOURCE/DRAIN STRESSORS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern. | 03-27-2014 |
20140312430 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate. | 10-23-2014 |
Patent application number | Description | Published |
20120023386 | Magnetic Memory Devices, Electronic Systems And Memory Cards Including The Same, Methods Of Manufacturing The Same, And Methods Of Controlling A Magnetization Direction Of A Magnetic Pattern - Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration. | 01-26-2012 |
20120135544 | Method of Fabricating Semiconductor Device and Apparatus for Fabricating the Same - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor. | 05-31-2012 |
20140183674 | MAGNETIC MEMORY DEVICES HAVING A UNIFORM PERPENDICULAR NONMAGNETIC RICH ANTISOTROPY ENHANCED PATTERN - Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration. | 07-03-2014 |
Patent application number | Description | Published |
20100209826 | Apparatus for processing photomask, methods of using the same, and methods of processing photomask - An apparatus and method for improving global flatness of a photomask is provided. The apparatus may include an adsorbing plate including vacuuming holes on one surface thereof, the adsorbing plate being adapted to adsorb the photomask thereon, a photomask supporting part including a plurality of supporting portions adapted to support the photomask and supporting arms on which the supporting portions are disposed, and a pressing plate including a pressing frame adapted to apply pressure to one surface of the photomask. | 08-19-2010 |
20110169495 | MONITORING MODULE INCLUDING E-FIELD-INDUCED ESD-SENSITIVE PATTERN AND PHOTOMASK INCLUDING THE MODULE - Provided are a monitoring module of an electrostatic discharge (ESD)-sensitive photomask, in which when an external electric field (E-field) exists, monitoring patterns are formed in the same direction as or a vertical direction to the external E-field, and a photomask including the module. The monitoring module includes a plurality of monitoring patterns, which are electrically isolated from one another and arranged at right angles to one another. At least one first monitoring pattern of the plurality of monitoring patterns is arranged in the same direction as an E-field existing outside the photomask. At least one second monitoring pattern of the plurality of monitoring patterns is arranged at substantially right angles to the first monitoring pattern in consideration of a direction in which charges move due to rotation of the photomask. | 07-14-2011 |
20130089814 | PELLICLE HAVING BUFFER ZONE AND PHOTOMASK STRUCTURE HAVING PELLICLE - A pellicle including a frame having a square shape; and a buffer zone in the frame, the buffer zone dividing a lower surface of the frame into a plurality of portions. | 04-11-2013 |
20130250286 | APPARATUS FOR MEASURING PATTERNS ON A REFLECTIVE PHOTOMASK - An apparatus for inspecting, measuring, or inspecting and measuring a reflective photomask may comprise a light illuminating part including a light source and beam shaping part; a stage configured to cause the light generated to be incident at an angle through the beam shaping part; and/or a light detector configured to receive optical image information of the photomask mounted on the stage. An apparatus for inspecting, measuring, or inspecting and measuring a reflective photomask may comprise a light illuminating part including a light source and configured to adjust a progress direction of light from the light source at an angle; a stage in a direction at which the light is irradiated from the light illuminating part at the angle and configured to mount the photomask; a slit plate between the light illuminating part and the stage; and/or a light detector configured to receive image information of the photomask. | 09-26-2013 |
20130251238 | METHODS OF ALIGNING OBJECTS AND APPARATUSES FOR PERFORMING THE SAME - A method of aligning an object may include obtaining a first actual image of a first pattern on the object, setting the first actual image as a first reference image, obtaining a second actual image of a second pattern on the object, comparing the second actual image with the first reference image to obtain first relative position difference values of the second actual image with respect to the first reference image, and converting the first relative position difference values into first absolute position difference values with respect to a reference point on the object. | 09-26-2013 |
Patent application number | Description | Published |
20110091762 | ELECTRODE ASSEMBLY FOR SECONDARY BATTERY, METHOD OF MANUFACTURING THE SAME AND SECONDARY BATTERY WITH THE SAME - An electrode assembly for a secondary battery, a method of manufacturing the electrode assembly and a secondary battery having the electrode assembly. The electrode assembly includes a plurality of electrode members arranged in a stacked shape along a baseline extending in one direction and a separation unit separating two adjacent electrode members. The separation unit includes three or more separators having a same winding center. | 04-21-2011 |
20110104541 | SECONDARY BATTERY AND METHOD OF MANUFACTURING THE SECONDARY BATTERY - A secondary battery and a method of manufacturing the secondary battery. A secondary battery includes an electrode assembly formed through winding a positive electrode plate including a positive electrode non-coating portion, a negative electrode plate including a negative electrode non-coating portion, and a separator between the positive and negative electrode plates. A part of the positive electrode non-coating portion and a part of the negative electrode non-coating portion are removed to form a positive electrode tab and a negative electrode tab at first and second ends, respectively, of the electrode assembly. | 05-05-2011 |
20110104550 | ELECTRODE ASSEMBLY FOR SECONDARY BATTERY AND SECONDARY BATTERY HAVING THE SAME - An electrode assembly for a secondary battery and a secondary battery having the same, the electrode assembly including electrode members disposed in a stack and divided into groups; and a first separator having folded portions disposed between the electrode members, and wound portions extending from the folded portions and wrapped around the groups. | 05-05-2011 |
20110123841 | ELECTRODE ASSEMBLY AND SECONDARY BATTERY INCLUDING THE SAME - An electrode assembly and a secondary battery including the same are disclosed. An electrode assembly includes a positive electrode including a positive electrode coating portion coated on a surface of a positive electrode collector; a negative electrode including a negative electrode coating portion coated on a surface of a negative electrode collector; and a separator between the positive and negative electrodes. The positive electrode and the negative electrode are stacked, and the positive electrode coating portion and the negative electrode coating portion on surfaces facing each other have a same area, or an area of the positive electrode coating portion is greater than an area of the negative electrode coating portion within a tolerance range. | 05-26-2011 |
20110129707 | SECONDARY BATTERY - A secondary battery including an electrode assembly. The electrode assembly includes a first electrode including a plurality of first electrode tabs extending to a side of the first electrode, a second electrode including a plurality of second electrode tabs extending to a side of the second electrode, and a separator between the first electrode and the second electrode and insulating the first electrode and the second electrode from one another. The electrode assembly is in a wound jelly roll shape. The plurality of first electrode tabs are in one of four quadrants formed by a long axis and a short axis of the wound electrode assembly. The plurality of second electrode tabs are in a different one of the four quadrants. | 06-02-2011 |
20110129711 | Secondary Battery - A secondary battery including: an electrode assembly including a plurality of first and second electrode plates, and a plurality of separators between the first and second electrode plates; a first electrode tab on the first electrode plate, and a second electrode tab on the second electrode plate; a case housing the electrode assembly, and the first and second electrode tabs; and first and second external lead terminals at an outer side of the case and electrically coupled to the first and second electrode tabs, respectively. | 06-02-2011 |
20130166233 | DEVICE FOR ESTIMATING A LIFETIME OF A SECONDARY BATTERY AND METHOD THEREOF - Embodiments of the present invention provide an accelerated lifetime estimation device for predicting the lifetime of a secondary battery, and a method thereof. The accelerated lifetime estimation device can accurately estimate a normal lifetime of the secondary battery while reducing an evaluation time period of the secondary battery. | 06-27-2013 |
20130268466 | SYSTEM FOR PREDICTING LIFETIME OF BATTERY - A system for predicting a lifetime of a battery cell, including a learning data input unit, the learning data input unit being configured to receive at least one learning measurement factor and at least one learning factor, a target data input unit, the target data input unit being configured to receive at least one target factor, a machine learning unit, the machine learning unit being coupled to the learning data input unit, the machine learning unit assigning weights to respective ones of the learning factors input to the learning data input unit, and a lifetime prediction unit, the lifetime prediction unit being coupled to the target data input unit and the machine learning unit, the lifetime prediction unit using the weights assigned by the machine learning unit to predict one or more characteristics indicative of the lifetime of the target battery cell. | 10-10-2013 |
Patent application number | Description | Published |
20120063521 | FRACTIONAL-N PHASE LOCKED LOOP, OPERATION METHOD THEREOF, AND DEVICES HAVING THE SAME - A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer. | 03-15-2012 |
20120262200 | HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT - A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code. | 10-18-2012 |
20130002954 | CLOCK GENERATION METHOD AND APPARATUS IN MULTIMEDIA SYSTEM - A clock generation method and apparatus in a multimedia system includes generating a first intermediate clock with multiple phases by multiplying a frequency of an input clock by a predetermined factor using a phase-locked loop or a delay-locked loop, generating a transmission clock by dividing a frequency of the first intermediate clock by 5, and generating a pixel clock used in the multimedia system using a frequency of the transmission clock. When the first intermediate clock with the multiple phases is used to generate the pixel clock corresponding to a color depth, the number of phase-locked loops or delay-locked loops necessary for frequency multiplication can be reduced. | 01-03-2013 |
20130259177 | DATA RECOVERY CIRCUIT AND OPERATION METHOD THEREOF - In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data. | 10-03-2013 |
20130268819 | DATA RECEIVER DEVICE AND TEST METHOD THEREOF - A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit. | 10-10-2013 |
20150033060 | CLOCK DATA RECOVERY CIRCUIT, TIMING CONTROLLER INCLUDING THE SAME, AND METHOD OF DRIVING THE TIMING CONTROLLER - Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller. | 01-29-2015 |
Patent application number | Description | Published |
20090174829 | LIQUID CRYSTAL DISPLAY APPARATUS - In the provided liquid crystal display apparatus, a first switching element receives a first data signal and a second switching element receives a second data signal having a polarity opposite that of the first data signal. A first pixel electrode is electrically connected to the first switching element to receive the first data signal and a second pixel electrode is electrically connected to the second switching element to receive the second data signal. The second pixel electrode faces the first pixel electrode and is electrically insulated from the first pixel electrode. A liquid crystal layer has liquid crystal molecules aligned in response to the first and second data signals applied to the first and second pixel electrodes, respectively. Thus, the liquid crystal display apparatus may prevent afterimages on a screen thereof and a flickering phenomenon. | 07-09-2009 |
20100025689 | THIN FILM TRANSISITOR ARRAY PANEL AND MANUFACTURING TMETHOD THEREOF - A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes. | 02-04-2010 |
20100103087 | THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY INCLUDING THE PANEL - A thin film transistor array panel according to an embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and extending in a first direction; a capacitive electrode separated from the gate line and elongated in a second direction; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line and including a drain electrode; a coupling electrode overlapping the capacitive electrode and connected to the drain electrode; and a pixel electrode including at least one first subpixel electrode connected to the drain electrode and a second subpixel electrode connected to the capacitive electrode and spaced apart from the at least first subpixel electrode by a gap that overlaps the capacitive electrode or the coupling electrode. | 04-29-2010 |
20100118247 | LIQUID CRYSTAL DISPLAY - A liquid crystal display includes a substrate, a pixel electrode disposed on the substrate and including a first subpixel electrode and a second subpixel electrode, and a common electrode facing the pixel electrode. The first subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to each other, the first oblique edges making an oblique angle with the first edge and the second edge and meeting the first edge. The second subpixel electrode comprises a first edge, a second edge disposed opposite the first edge, and two first oblique edges substantially parallel to or substantially perpendicular to the first oblique edges of the first subpixel electrode, the first oblique edges of the second subpixel electrode meeting the first edge of the second subpixel electrode. The first edge of the first subpixel electrode is adjacent to the first edge of the second subpixel electrode, and a length of the first edge of the first subpixel electrode is different from a length of the first edge of the second subpixel electrode. The first oblique edges of the first subpixel electrode are offset from the first oblique edges of the second subpixel electrode. | 05-13-2010 |
20110012941 | LIQUID CRYSTAL DISPLAY PANEL, METHOD FOR DRIVING THE SAME, AND LIQUID CRYSTAL DISPLAY APPARATUS USING THE SAME - The disclosure describes a liquid crystal display panel including a plurality of sub-pixels, a plurality of thin film transistors, a plurality of data lines, and a plurality of gate lines. Each of the sub-pixels has first and second gray scale regions which are split up and down and have different areas, first and second gray scale regions of one sub-pixel having a staggered arrangement with respect to those of an adjacent sub-pixel. Thin film transistors are connected to first and second gray scale regions so that first gray scale regions are driven when one of gate lines is driven and the second gray scale regions are driven when another gate line is driven. | 01-20-2011 |
20110211137 | LIQUID CRYSTAL DISPLAY - A pixel electrode and a direction control electrode capacitively coupled to the pixel electrode are provided in a pixel. A pixel thin film transistor is connected to a gate line, a data line, and the pixel electrode. A direction control electrode thin film transistor is connected to a previous gate line, a previous data lines or a next data line, and the direction control electrode. The gate lines are supplied with scanning signals, and each scanning signal includes first and second pulses in a frame. The first pulse of a scanning signal is synchronized with the second pulse of a previous scanning signal. | 09-01-2011 |
Patent application number | Description | Published |
20090246914 | Semiconductor package and method of manufacturing the same - A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the through hole of the film substrate. Circuit wires may be formed on the film substrate to contact the bumps of the semiconductor chip. | 10-01-2009 |
20100187686 | SEMICONDUCTOR PACKAGE COMPRISING ALIGNMENT MEMERS - A semiconductor package comprising alignment members is provided. The semiconductor package includes a semiconductor die, first connection terminals disposed on a first surface of the semiconductor die, and a tape substrate including a substrate portion, and second connection terminals disposed on the substrate portion and disposed corresponding to the first connection terminals. The semiconductor package further includes a first alignment member disposed on the first surface of the semiconductor die, and a second alignment member disposed on the substrate portion of the tape substrate and disposed corresponding to the first alignment member. | 07-29-2010 |
20120138968 | SEMICONDUCTOR PACKAGE AND DISPLAY PANEL ASSEMBLY HAVING THE SAME - Provided are a semiconductor package with a reduced lead pitch, and a display panel assembly having the semiconductor package. The semiconductor package includes a film having a hole formed therein, a plating pattern formed under the film and forming a wire; a semiconductor chip placed in the hole and electrically connected to the plating pattern; and a first passivation layer formed at a side opposite to the semiconductor chip about the plating pattern and protecting the plating pattern. | 06-07-2012 |
20140054793 | Chip on Film (COF) Substrate, COF Package and Display Device Including the Same - A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film. | 02-27-2014 |
20140246687 | CHIP ON FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME - A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads. | 09-04-2014 |
20140327148 | CHIP ON FILM PACKAGE INCLUDING DISTRIBUTED VIA PLUGS - A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length, first via plugs penetrating the film substrate and connected to first ends of the first leads, and second via plugs penetrating the film substrate and connected to first ends of the second leads, and first connection leads on a second surface of the film substrate facing the first surface, the first connection leads having first ends connected to the first via plugs, and second connection leads on the second surface of the film substrate, the second connection leads having first ends electrically connected to the second via plugs. | 11-06-2014 |
Patent application number | Description | Published |
20100155810 | MULTI-LAYER NONVOLATILE MEMORY DEVICES HAVING VERTICAL CHARGE STORAGE REGIONS - Some embodiments of the present invention provide nonvolatile memory devices including a plurality of intergate insulating patterns and a plurality of cell gate patterns that are alternately and vertically stacked on a substrate, an active pattern disposed on the substrate, the active pattern extending upwardly along sidewalls of the intergate insulating patterns and the cell gate patterns, a plurality of charge storage patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, the plurality of the charge storage patterns being separated from each other, tunnel insulating patterns disposed between the plurality of cell gate patterns and the active pattern, respectively, and the tunnel insulating patterns extending to be directly connected to each other and a plurality of blocking insulating patterns disposed between the plurality of cell gate patterns and the plurality of charge storage patterns, respectively. A sidewall of the cell gate pattern may be recessed laterally so that an undercut region is defined and the charge storage pattern is disposed in the undercut region. | 06-24-2010 |
20100178759 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 07-15-2010 |
20100248457 | METHOD OF FORMING NONVOLATILE MEMORY DEVICE - Provided is a method of forming a nonvolatile memory device. The method may include alternatingly stacking n number of dielectric layers and n number of conductive layers on a substrate, forming a non-photosensitive pattern on the alternatingly stacked dielectric layers and conductive layers, etching the i-th conductive layer and i-th dielectric (2≦i≦n, i is a natural number indicating a stacking order of the conductive layers and the dielectric layers) by using the non-photosensitive pattern as an etch mask, laterally etching a sidewall of the non-photosensitive pattern and etching the i-th conductive layer, (i−1)-th conductive layer, i-th dielectric layer and (i−1)-th dielectric layer by using the etched non-photosensitive pattern as an etch mask. | 09-30-2010 |
20110101443 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern. | 05-05-2011 |
20130005104 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - Provided are a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a stacked structure, a semiconductor pattern, an information storage layer, and a fixed charge layer. The stacked structure may be disposed over a semiconductor substrate. The stacked structure may include conductive patterns and interlayer dielectric patterns alternately stacked therein. The semiconductor pattern may be connected to the semiconductor substrate by passing through the stacked structure. The information storage layer may be disposed between the semiconductor pattern and the conductive patterns. The fixed charge layer may be disposed between the semiconductor pattern and the interlayer dielectric pattern. The fixed charge layer may include fixed charges. Electrical polarity of the fixed charges may be equal to electrical polarity of majority carriers of the semiconductor pattern. | 01-03-2013 |
20130273728 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 10-17-2013 |
Patent application number | Description | Published |
20080234383 | Novel Compounds, Isomer Thereof, or Pharmaceutically Acceptable Salts Thereof as Vanilloid Receptor Antagonist; and Pharmaceutical Compositions Containing the Same - This present invention relates to novel compounds, isomer thereof or pharmaceutically acceptable salts thereof as vanilloid receptor (Vanilloid Receotor 1; VR1; TRPV1) antagonist; and a pharmaceutical composition containing the same. The present invention provides a pharmaceutical composition for preventing or treating a disease such as pain, migraine, arthralgia, neuralgia, neuropathies, nerve injury, skin disorder, urinary bladder hypersensitiveness, irritable bowel syndrome, fecal urgency, a respiratory disorder, irritation of skin, eye or mucous membrane, stomach-duodenal ulcer, inflammatory diseases, ear disease, and heart disease. | 09-25-2008 |
20090036501 | 2-Cyclopenten-1-One Oxime Derivatives Inhibiting Production of TNF-Alpha - 2-cyclopenten-1-one oxime derivatives represented by Formula (I), or pharmaceutically acceptable salts thereof inhibit the production of TNF-α or PDE4, and therefore show therapeutic effect in inflammatory or immunological disorders mediated through TNF-α or PDE4. | 02-05-2009 |
20090105258 | NOVEL COMPOUNDS, ISOMER THEREOF, OR PHARMACEUTICALLY ACCEPTABLE SALTS THEREOF AS VANILLOID RECEPTOR ANTAGONIST; AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME - This present invention relates to novel compounds, isomer thereof or pharmaceutically acceptable salt thereof as vanilloid receptor (Vanilloid Receptor 1; VR1; TRRPV1) antagonist; and a pharmaceutical composition containing the same. The present invention provides a pharmaceutical composition for preventing or treating a disease such as pain, migraine, arthralgia, neuralgia, neuropathies, nerve injury, skin disorder, urinary bladder hypersensitiveness, irritable bowel syndrome, fecal urgency, a respiratory disorder, irritation of skin, eye or mucous membrane, stomach-duodenal ulcer, inflammatory diseases, ear disease, and heart disease. | 04-23-2009 |
20130158025 | NOVEL COMPOUND ACTING AS A CANNABINOID RECEPTOR-1 INHIBITOR - Disclosed is a novel compound acting as a cannabinoid receptor 1 inhibitor, a prodrug thereof, an isomer thereof, a pharmaceutically acceptable salt thereof, a hydrate thereof or a solvate thereof. The novel compound or the like is useful for preventing or treating diseases mediated by the cannabinoid receptor-1. | 06-20-2013 |
20140011881 | NOVEL COMPOUNDS, ISOMER THEREOF, OR PHARMACEUTICALLY ACCEPTABLE SALTS THEREOF AS VANILLOID RECEPTOR ANTAGONIST; AND PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME - This present disclosure relates to novel compounds, isomer thereof or pharmaceutically acceptable salts thereof as vanilloid receptor (Vanilloid Receptor 1; VR1; TRPV1) antagonist; and a pharmaceutical composition containing the same. | 01-09-2014 |
20140234241 | NOVEL BENZOIC ACID AMIDE COMPOUND - The present invention relates to a novel benzoic acid amide derivative compound, isomers thereof, pharmaceutically acceptable salts thereof, prodrugs thereof, hydrates thereof, or solvates thereof. The novel compound has excellent skin whitening effects. | 08-21-2014 |
Patent application number | Description | Published |
20110261307 | LIQUID CRYSTAL DISPLAY - In a liquid crystal display, a first alignment layer formed on a first substrate includes a first region aligned in a first direction and a second region aligned in a second direction opposite to the first direction, and a second alignment layer formed on a second substrate facing the first substrate includes a third region aligned in a third direction different from the first direction and a fourth region aligned in a fourth direction opposite to the third direction. The liquid crystal molecules interposed between the first and second alignment layers are aligned in different directions in different domains defined by the first to fourth regions. A pixel electrode includes an extension part extending in at least one of the first to fourth directions. The aperture ratio and the light transmittance of the liquid crystal display are improved. | 10-27-2011 |
20120154727 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display panel including pixels, wherein at least one of the pixels includes a first sub-pixel charged with a first voltage and a second sub-pixel charged with a second voltage lower than the first voltage, a first substrate including a first sub-pixel electrode of the first sub-pixel and a second sub-pixel electrode of the second sub-pixel, a first alignment layer aligned in first and second directions in each of the first and second sub-pixels, a second alignment layer aligned in third and fourth directions in each of the first and second sub-pixels to form a plurality of domains in each of the first and second sub-pixels, and a liquid crystal layer disposed between the first and second alignment layers, wherein the first sub-pixel electrode includes a plurality of slits formed substantially parallel to a liquid crystal alignment direction in each of the domains of the first sub-pixel electrode. | 06-21-2012 |
20140104528 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - Provided is a display panel including: an array substrate; an opposite substrate facing the array substrate and including a second base substrate and a common electrode disposed on the second base substrate; and a liquid crystal layer disposed between the array substrate and the opposite substrate. The array substrate includes: a first base substrate disposed in a display area and a non-display area; a photosensitive polymer organic layer disposed in a first non-display area and extending to a pad area, the photosensitive polymer organic layer having a taper shape at an end portion of the first non-display area; a thin film transistor disposed on the first base substrate in the display area; a pixel electrode connected to the thin film transistor; and a signal input pad connected to the thin film transistor and disposed on the photosensitive polymer organic layer in the pad area. | 04-17-2014 |
20150085227 | LIQUID CRYSTAL DISPLAY HAVING IMPROVED VIEWING ANGLE AND CONTRAST RATIO AND METHOD OF MANUFACTURING THE SAME - A display crystal display includes a liquid crystal display panel, a polarizing plate disposed on at least one surface of the liquid crystal display panel, and a retardation layer disposed between the liquid crystal display panel and the polarizing plate. | 03-26-2015 |
Patent application number | Description | Published |
20080282229 | Apparatus and method of detecting errors in embedded software - A method and apparatus for detecting errors in an application software of an embedded system are provided. The method of detecting errors in an application software includes determining a development language of the application software and an operating system on which the application software is executed; replacing an error detection syntax inserted in order to examine an error in a predetermined function of the application software, with an error detection syntax according to the result of the determination; and performing exception handling for an error occurring in the function according to the result of the replacement, and logging error information according to the exception handling. According to the method and apparatus, an error can be automatically detected and logged irrespective of a development language and an operating system. | 11-13-2008 |
20100146168 | System and method of inter-connection between components using software bus - A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port. | 06-10-2010 |
20100312977 | Method of managing memory in multiprocessor system on chip - Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location. | 12-09-2010 |
20110072231 | Device, method and computer-readable medium relocating remote procedure call data in heterogeneous multiprocessor system on chip - Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory. | 03-24-2011 |