Shin, Icheon-Si
Beom Ju Shin, Icheon-Si KR
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20110317494 | PIPE LATCH CIRCUIT OF MULTI-BIT PREFETCH-TYPE SEMICONDUCTOR MEMORY DEVICE WITH IMPROVED STRUCTURE - Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit of the present invention comprises: a first latch circuit for latching pre-fetched plural bits of input data from global input/output lines; a first multiplexing circuit comprises a first multiplexer for selecting a certain input data from first group of the input data in response to a first selection control signal and a second multiplexer for selecting a certain input data from second group of the input data in response to a second selection control signal; a second multiplexing circuit for setting a sequence of output data from the first multiplexing circuit in response to a third selection control signal; and a second latch circuit comprises a third latch for latching a first output data from the second multiplexing circuit in response to a first output latch control signal and a fourth latch for latching a second output data from the second multiplexing circuit in response to a second output latch control signal. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order. | 12-29-2011 |
20120002487 | NONVOLATILE MEMORY APPARATUS AND METHOD FOR PROCESSING CONFIGURATION INFORMATION THEREOF - A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period. | 01-05-2012 |
20120110401 | SYSTEM AND METHOD OF SENSING DATA IN A SEMICONDUCTOR DEVICE - A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias generating unit configured to generate the plurality of read bias signals whose voltage levels are adjusted based on the code value of the bias control code. | 05-03-2012 |
Chang-Hun Shin, Icheon-Si KR
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20150176128 | Substrate Processing Apparatus - There is provided a substrate processing apparatus including: a chamber providing an internal space, in which a substrate is transferred through a passage and a process is performed on the substrate, and having a supply port supplying a gas to the substrate; and a susceptor installed in the internal space and including a heating region heating the substrate and a pre-heating region pre-heating the gas supplied from the supply port. | 06-25-2015 |
20150187560 | Cyclic Deposition Method for Thin Film Formation, Semiconductor Manufacturing Method, and Semiconductor Device - A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof. | 07-02-2015 |
Chang-Hyup Shin, Icheon-Si KR
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20150029779 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode. | 01-29-2015 |
Ji Hye Shin, Icheon-Si KR
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20150380429 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer. | 12-31-2015 |
Wan-Cheul Shin, Icheon-Si KR
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20090218696 | SEMICONDUCTOR DEVICE INCLUDING A PADDING UNIT - A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed between the bit lines and an upper padding layer. The upper layer as a slit formed therein. The lower padding layer prevents damage to the bit lines due to plasma gas entering through the slit. | 09-03-2009 |