Patent application number | Description | Published |
20090134935 | ANTI-FUSE REPAIR CONTROL CIRCUIT FOR PREVENTING STRESS ON CIRCUIT PARTS - The present invention relates to an anti-fuse repair control circuit which regulates transmission of a power voltage and a back-bias voltage that are converted to repair an anti-fuse to a circuit part. As such, the present invention prevents the influence of a high power voltage or a low back-bias voltage on a circuit part such as a cell, a peripheral circuit, or a core region during an anti-fuse repair. The anti-fuse repair control circuit includes an anti-fuse repair enabling part providing an anti-fuse repair enabling signal corresponding to a repair of an anti-fuse; a power voltage control part controlling transmission of a power voltage to a first circuit part according to an enablement state of the anti-fuse repair enabling signal; and a back-bias voltage control part controlling transmission of a back-bias voltage to a second circuit part according to the enablement state of the anti-fuse repair enabling signal. | 05-28-2009 |
20090141577 | ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME - In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled. | 06-04-2009 |
20090251985 | SEMICONDUCTOR MEMORY APPARATUS - A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals. | 10-08-2009 |
20100032669 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING TEST MODES WITHOUT STOPPING TEST - A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state. | 02-11-2010 |
20100142299 | ANTI-FUSE REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING DRAM HAVING THE SAME - In an anti-fuse repair control circuit, a semiconductor memory device is integrated into a multi-chip package to perform an anti-fuse repair. An anti-fuse repair control circuit includes a data mask signal input circuit, a cell address enable unit a repair enable unit, and a repair unit. The data mask signal input circuit receives and outputs a data mask signal upon receiving a test control signal for an anti-fuse repair. The cell address enable unit receives an anti-fuse repair address to enable a cell address of an anti-fuse cell to be repaired upon receiving the data mask signal outputted from the data mask signal input circuit. The repair enable unit codes the cell address and output a repair enable signal and a drive signal according to whether or not an anti-fuse cell corresponding to the cell address is enabled. The repair unit supplies a repair voltage to the anti-fuse cell when the repair enable signal, the address, and the drive signal are enabled. | 06-10-2010 |
20110292746 | DATA TRANSFER CIRCUIT, METHOD THEREOF, AND MEMORY DEVICE INCLUDING DATA TRANSFER CIRCUIT - A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change. | 12-01-2011 |
Patent application number | Description | Published |
20090046524 | MULTI-COLUMN DECODER STRESS TEST CIRCUIT - The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals. | 02-19-2009 |
20090059691 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF - A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output switches in up and down mats according to up/down information addresses during a read operation mode, a multi-mode decoding section that simultaneously activates multi mat selection signals corresponding to one of the up mats and one of the down mats according to row addresses in an active operation mode, and a mat control section that receives the up and down mat input/output switch control signals and the multi mat selection signals and enables word lines and input/output switches in the mats corresponding to the signals. | 03-05-2009 |
20090207673 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST - A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals. | 08-20-2009 |
20090230986 | SEMICONDUCTOR INTEGRATED CIRCUIT, FUSE CIRCUIT FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD OF THE SAME - A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal. | 09-17-2009 |
20120039137 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH MULTI TEST - A semiconductor integrated circuit includes a multi-mode control signal generating unit configured to control an activation of a up/down mat I/O switch control signal, which controls I/O switches in a up/down mat, according to a multi-test mode signal and a read/write discriminating signal, a multi-mode decoder configured to output multi-mat select signals to simultaneously activate a plurality of mats according to a multi-test mode active write signal, and a mat controller configured to enable word lines and the I/O switches according to the up/down mat I/O switch control signal and the multi-mat select signals. | 02-16-2012 |
Patent application number | Description | Published |
20090168840 | Thermal data output circuit and multi chip package using the same - A temperature data output circuit is provided which is capable of outputting a temperature signal which is enabled when an internal temperature of at least one of the semiconductor memory chips mounted on a multi chip package exceeds a predetermined temperature. | 07-02-2009 |
20120081823 | PROTECTION CIRCUIT OF SEMICONDUCTOR APPARATUS - An internal circuit protection circuit includes a voltage comparison unit and an internal circuit protection unit. The voltage comparison unit is configured to compare an external driving voltage applied from outside with a reference clamp voltage and output a comparison signal. The internal circuit protection unit is configured to adjust a level of the external driving voltage to a lower level than that of the reference clamp voltage, in response to the comparison signal. | 04-05-2012 |
20120249214 | DRIVER CIRCUIT OF SEMICONDUCTOR APPARATUS AND METHOD FOR CONTROLLING THE SAME - A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal. | 10-04-2012 |
20120257468 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a transmission line configured to transmit a fuse enable signal for performance of a repair operation; a first repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a first repair enable signal for performing a repair operation for a first bank; and a second repair enable signal generation unit configured to receive the fuse enable signal through the transmission line and generate a second repair enable signal for performing a repair operation for a second bank. | 10-11-2012 |
20130114358 | ADDRESS DECODING METHOD AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A semiconductor memory device includes: a strobe clock generator configured to generate a strobe clock signal having a delay time controlled according to a plurality of test mode signals which are selectively enabled in response to a read signal or write signal; an internal address generator configured to latch an address in response to a first level of the strobe clock signal, and generate an internal address by decoding the address in response to a second level of the strobe clock signal; and an output enable signal generator configured to decode the internal address and generate output enable signals which are selectively enabled. | 05-09-2013 |
20140050035 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode. | 02-20-2014 |