Patent application number | Description | Published |
20090032858 | LAYOUT AND STRUCTURE OF MEMORY - A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on. | 02-05-2009 |
20090040823 | FLASH MEMORY - A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on. | 02-12-2009 |
20110065253 | MANUFACTURING METHOD FOR DOUBLE-SIDE CAPACITOR OF STACK DRAM - A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors. | 03-17-2011 |
20110076828 | METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY - A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes. | 03-31-2011 |
20110081763 | PROCESS USING OXIDE SUPPORTER FOR MANUFACTURING A CAPACITOR LOWER ELECTRODE OF A MICRO STACKED DRAM - A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer. | 04-07-2011 |
20110086490 | SINGLE-SIDE IMPLANTING PROCESS FOR CAPACITORS OF STACK DRAM - A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film. | 04-14-2011 |
20110090617 | CAPACITOR ELECTRODE, CAPACITOR STRUCTURE AND METHOD OF MAKING THE SAME - A method of fabricating a capacitor electrode. A stack structure is formed on a substrate, and the stack structure includes a first conductive layer, a first sacrificial layer, and a second sacrificial layer. The stack structure includes a first sidewall and a second sidewall facing the first sidewall. A conductive sidewall is formed on the first sidewall and the second sidewall to electrically connect the first conductive layer to the second conductive layer. Finally, the first and the second sacrificial layers are removed. | 04-21-2011 |
20110092044 | METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY - A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer. | 04-21-2011 |
20110127574 | DEVICE FOR PREVENTING CURRENT-LEAKAGE - A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem. | 06-02-2011 |
20130252397 | MANUFACTURING METHOD FOR HIGH CAPACITANCE CAPACITOR STRUCTURE - A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers. | 09-26-2013 |