Patent application number | Description | Published |
20120091549 | FORMATION OF EMBEDDED MICRO-LENS - Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction. | 04-19-2012 |
20130034929 | Method for Forming CMOS Image Sensors - A method includes forming a blocking layer over a substrate, and etching the blocking layer to form a trench in the blocking layer. A dielectric layer is formed, wherein the dielectric layer comprises a first portion over the blocking layer, and a second portion in the trench. After the step of forming the dielectric layer, an implantation is performed to implant an impurity into the substrate to form a deep well region. After the implantation, the dielectric layer and the blocking layer are removed. | 02-07-2013 |
20130037958 | CMOS Image Sensor and Method for Forming the Same - An integrated circuit structure includes an interconnect structure that includes a plurality of metal layers, wherein the interconnect structure is under a semiconductor substrate. A metal pad is formed in one of the plurality of metal layers. A dielectric pad extends from a bottom surface of the semiconductor substrate up into the semiconductor substrate. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate and the dielectric pad. An edge of the semiconductor substrate in the opening is vertically aligned to an edge of the dielectric pad in the opening. The opening stops on a top surface of the metal pad. A dielectric spacer is disposed in the opening, wherein the dielectric spacer is formed on the edge of the semiconductor substrate and the edge of the dielectric pad. | 02-14-2013 |
20130327921 | IMAGE DEVICE AND METHODS OF FORMING THE SAME - A method of forming of an image sensor device includes a substrate having a pixel region and a periphery region. A plurality of first trenches is etched in the periphery region. Each of the first trenches has a depth D | 12-12-2013 |
20140264709 | Interconnect Structure for Connecting Dies and Methods of Forming the Same - A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers. | 09-18-2014 |
20140264719 | Varied STI Liners for Isolation Structures in Image Sensing Devices - An integrated circuit device incorporating a plurality of isolation trench structures configured for disparate applications and a method of forming the integrated circuit are disclosed. In an exemplary embodiment, a substrate having a first region and a second region is received. A first isolation trench is formed in the first region, and a second isolation trench is formed in the second region. A first liner layer is formed in the first isolation trench, and a second liner layer is formed in the second isolation trench. The second liner layer has a physical characteristic that is different from a corresponding physical characteristic of the first liner layer. An implantation procedure is performed on the second isolation trench and the second liner layer formed therein. The physical characteristic of the second liner layer may be selected to enhance an implantation depth or an implantation uniformity compared to the first liner layer. | 09-18-2014 |
20140264929 | Interconnect Structure for Stacked Device - A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers. | 09-18-2014 |
20140264947 | Interconnect Apparatus and Method - A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask. | 09-18-2014 |
20150069619 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. | 03-12-2015 |