Patent application number | Description | Published |
20080196624 | Antireflective transparent zeolite hardcoat, method for fabricating the same - An antireflective transparent zeolite hardcoat and fabrication method thereof. The transparent zeolite hardcoat comprises a zeolite nanostructure made of zeolite nanocrystals vertically stacked into a porous structure on a substrate, wherein the porosity increases with structure height, thereby providing a smooth refractive index transition. | 08-21-2008 |
20080206456 | Antireflective transparent zeolite hardcoat, method for fabricating the same - An antireflective transparent zeolite hardcoat and fabrication method thereof. The transparent zeolite hardcoat comprises a zeolite nanostructure made of zeolite nanocrystals vertically stacked into a porous structure on a substrate, wherein the porosity increases with structure height, thereby providing a smooth refractive index transition. | 08-28-2008 |
20080211997 | POLARIZING PLATES AND LIQUID CRYSTAL DISPLAYS COMPRISING THE SAME - A polarizing plate is provided. The polarizing plate includes a polarizing film, a first protective film and a second protective film respectively disposed on both sides of the polarizing film, and a polyimide optical compensation film having thickness direction retardation (Rth) or both, in-plane retardation (R0) and thickness direction retardation (Rth) disposed on the first protective film. The invention also provides a liquid crystal display including the polarizing plate. | 09-04-2008 |
20090053891 | Method for fabricating a semiconductor device - A method for fabricating a semiconductor device for preventing a poisoned via is provided. A substrate with a conductive layer formed thereon is provided. A composite layer is formed over the substrate and the conductive layer, wherein the composite layer comprises a dielectric layer and a spin-on-glass layer. A via hole is formed through the composite layer, wherein the via hole exposes a surface of the conductive layer. A protection layer is formed on a sidewall of the via hole so as to prevent out-gassing from the spin-on-glass layer. A barrier layer is formed on the protection layer and the conductive layer within the via hole. And a metal layer is deposited on the barrier layer within the via hole to fill the via hole. | 02-26-2009 |
20090149564 | TRANSPARENT FLEXIBLE FILM AND FABRICATION METHOD THEREOF - A transparent flexible film is provided, formed by curing a composition, comprising: about 40-75 parts by weight of a clay; about 15-45 parts by weight of a water-soluble polymer; about 1-10 parts by weight of a mono-functional acrylic oligomer of formula (I), wherein n | 06-11-2009 |
20090236665 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 09-24-2009 |
20090236681 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 09-24-2009 |
20090279176 | ANTIGLARE FILM AND MANUFACTURING METHOD THEREOF - The invention provides an antiglare film. A resin layer is disposed on a substrate. Micro-aggregates are distributed in an interior and over a surface of the resin layer. Each of the micro aggregates has a size of 0.1-3 μm and is formed by aggregating aggregated nano-particles. The micro-aggregates distributing over the surface result in a surface roughness of the resin layer. The weight ratio of the resin layer to the micro-aggregates is 1:0.1-0.7. | 11-12-2009 |
20100181639 | SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF - A semiconductor device is provided. The semiconductor device comprises an epitaxial layer disposed on a semiconductor substrate, a plurality of electronic devices disposed on the epitaxial layer and a trench isolation structure disposed between the electric devices. The trench isolation structure comprises a trench in the epitaxial layer and the semiconductor substrate, an oxide liner on the sidewall and bottom of the trench, and a doped polysilicon layer filled in the trench. Moreover, a zero bias voltage can be applied to the doped polysilicon layer. The trench isolation structure can be used for isolating electronic devices having different operation voltages or high-voltage devices. | 07-22-2010 |
20110062500 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 03-17-2011 |
20110117709 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively. | 05-19-2011 |
20120056295 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask. | 03-08-2012 |
20120112329 | CHIP PACKAGE - An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof. | 05-10-2012 |
20120168211 | SUBSTRATE ASSEMBLY CONTAINING CONDUCTIVE FILM AND FABRICATION METHOD THEREOF - A substrate assembly containing a conductive film and a fabrication method thereof are provided. The substrate assembly includes a polymer substrate, a surface treatment layer formed on the polymer substrate and a conductive film formed on the surface treatment layer, wherein the conductive film is formed by sintering a metal conductive ink and the surface treatment layer is formed from a composite material of an auxiliary filler and a polymer. The auxiliary filler in the surface treatment layer can deliver energy into the metal conductive ink for sintering the conductive metal ink. | 07-05-2012 |