Patent application number | Description | Published |
20130047056 | FLASH MEMORY DEVICE WITH RECTIFIABLE REDUNDANCY AND METHOD OF CONTROLLING THE SAME - A flash memory device connected to a host includes: a flash memory; and a control circuit comprising a first error correcting code unit and a second error correcting code unit. The data length of a redundancy generated by the second error correcting code unit is longer than the data length of a redundancy generated by the first error correcting code unit. The first error correcting code unit is adopted to process with a data transmitted to the flash memory from the host when a damage risk of the flash memory is lower than a specific value; and the first and second error correcting code units are adopted to process with the data transmitted to the flash memory from the host when the damage risk of the flash memory is higher than the specific value. | 02-21-2013 |
20140133225 | DATA COMPENSATING METHOD FOR FLASH MEMORY - A data compensating method for a flash memory is provided. Firstly, a first threshold voltage distribution curve of the cells of the flash memory with a first storing state is acquired. Then, a second threshold voltage distribution curve of the cells of the flash memory with a second storing state is acquired. Then, a first occurrence probability of a first type ICI pattern of the first storing state is calculated according to a statistic voltage range and the first threshold voltage distribution curve. A second occurrence probability of the first type ICI pattern of the second storing state is acquired according to the statistic voltage range and the second threshold voltage distribution curve. During a read cycle, storing states of central cells corresponding to the first type ICI pattern are compensated according to the first occurrence probability and the second occurrence probability. | 05-15-2014 |
20140136924 | METHOD AND SYSTEM FOR DETERMINING STORING STATE OF FLASH MEMORY - A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage. | 05-15-2014 |
20140149828 | SOLID STATE DRIVE AND JOINT ENCODING/DECODING METHOD THEREOF - A joint encoding/decoding method for a solid state drive is provided. Firstly, a data-writing process is implemented for encoding a user data by a hard codec and a soft codec respectively, thereby generating a first number of parity bits and a second number of parity bits. Then, the user data, the first number of parity bits and the second number of parity bits are written into a flash memory module. Then, a data-reading process is implemented for decoding the user data by the hard codec according to the first number of parity bits. If the user data is successfully decoded, the user data is outputted. If the user data is unsuccessfully decoded, a step of decoding the user data by the soft codec according to the second number of parity bits is performed. | 05-29-2014 |
20140313822 | GROUP CLASSIFICATION METHOD FOR SOLID STATE STORAGE DEVICE - A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table corresponding to a first neighboring cell. Then, M | 10-23-2014 |
20140365172 | METHOD FOR ESTIMATING DISTRIBUTION CURVE OF STORING STATE OF SOLID STATE STORAGE DEVICE - A method for estimating a distribution curve of a first storing state of a solid state storage device includes the following steps. Firstly, plural threshold voltage intervals are provided. Numbers of cells within respective threshold voltage intervals are calculated. A location parameter interval is determined according to the numbers of cells within the threshold voltage intervals. The percentages of the cells within respective threshold voltage intervals are determined, and thus a distribution curve table is established. Then, m candidate location parameters within the location parameter interval are determined, and n candidate scale parameters are set. According to the m candidate location parameters and the n candidate scale parameters, m×n candidate Gaussian distribution curves are determined. A first Gaussian distribution curve selected from the m×n candidate Gaussian distribution curves is defined as the distribution curve. | 12-11-2014 |
20150106667 | SOLID STATE STORAGE DEVICE AND CONTROLLING METHOD THEREOF - A solid state storage device and controlling method thereof are provided, and the method includes following steps. Data is programmed into a flash memory module by using a first programming scheme. A data error parameter of the flash memory module is determined. If the data error parameter is greater than an error predefine value, the data is programmed into the flash memory module by using a second programming scheme. The first programming scheme and the second programming scheme are respectively mapping to a first threshold voltage frame and a second threshold voltage frame, and voltage interval of the second threshold voltage frame is broader than voltage interval of the first threshold voltage frame. | 04-16-2015 |
20150124533 | SOLID STATE STORAGE DEVICE AND SENSING VOLTAGE SETTING METHOD THEREOF - A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values. | 05-07-2015 |