Patent application number | Description | Published |
20080239728 | LIGHT CONTROL DEVICE HAVING MODIFIED PRISM STRUCTURE - The light control device provides fillings in the valleys of the prism elements, be it uniformly or non-uniformly arranged, which is made of UV and/or thermal curable resins of an appropriate refractive index different from that of the prism elements. The optical performance of the original prism elements can be altered by the following approaches. First, the refractive index of the fillings can be appropriately chosen. Second, the fillings can be up to an appropriate height (but never overruns the surrounding prism elements). Third, the distribution of the height or the refractive index of the fillings across the light emission plane can be “patterned,” that is, in accordance with the planar light intensity distribution produced by the light source. | 10-02-2008 |
20100033281 | PRECISE MULTI-POLE MAGNETIC COMPONENT - A method is provided to manufacture a precise multi-pole magnetic component for using in magnetic encoders. A special layout of the circuit pattern is designed and formed on a printed circuit board (PCB). Alternate and regular magnetic field is induced according to Ampere's law after a current flowing through the circuit on the PCB. The multi-pole magnetic component with fine magnetic pole pitch is achieved by forming the high-density circuit patterns on a substrate using the PCB technology. | 02-11-2010 |
20130342430 | COLOR SEQUENTIAL IMAGE METHOD AND SYSTEM THEREOF - A color sequential image method for displaying images using two color fields includes analyzing and sorting percentages of a plurality of colors constituting an input color image, in which a first color possesses a most percentage, a second color possesses a middle percentage, and a third color possesses a third percentage. The method further includes forming a first color field image according to the first color and the third color, and a second color field image according to the second color and the third color. | 12-26-2013 |
Patent application number | Description | Published |
20150055402 | NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE - Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer. | 02-26-2015 |
20150055426 | NOVEL SENSE AMPLIFIER SCHEME - A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated. | 02-26-2015 |
20150146480 | NOVEL 3D STRUCTURE FOR ADVANCED SRAM DESIGN TO AVOID HALF-SELECTED ISSUE - Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer. | 05-28-2015 |
20150162052 | THREE-DIMENSIONAL STATIC RANDOM ACCESS MEMORY DEVICE STRUCTURES - Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell. | 06-11-2015 |
20150243350 | NOVEL SENSE AMPLIFIER SCHEME - A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines. | 08-27-2015 |
Patent application number | Description | Published |
20100213440 | Silicon-Quantum-Dot Semiconductor Near-Infrared Photodetector - A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response. | 08-26-2010 |
20120256181 | POWER-GENERATING MODULE WITH SOLAR CELL AND METHOD FOR FABRICATING THE SAME - The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation. | 10-11-2012 |
20140008726 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface. | 01-09-2014 |
20140065754 | METHOD FOR FABRICATING POWER-GENERATING MODULE WITH SOLAR CELL - The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit. | 03-06-2014 |
20140131716 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate. | 05-15-2014 |
20140264271 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots. | 09-18-2014 |
Patent application number | Description | Published |
20080299741 | Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation - An etching solution, a method of surface modification of a semiconductor substrate and a method of forming shallow trench isolation are provided. The etching solution is used for surface modifying the semiconductor substrate. The etching solution includes an oxidant and an oxide remover. The semiconductor substrate is oxidized to a semiconductor oxide by the oxidant, and the oxide remover subtracts the semiconductor oxide. | 12-04-2008 |
20110075486 | CHARGE TRAPPING MEMORY CELL HAVING BANDGAP ENGINEERED TUNNELING STRUCTURE WITH OXYNITRIDE ISOLATION LAYER - A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes. | 03-31-2011 |
20150187578 | METHOD OF FORMING SILICON LAYER, AND METHOD OF MANUFACTURING FLASH MEMORY - A method of manufacturing a flash memory is provided. In the method, a hydrogen treatment is performed on a substrate, on which a polysilicon gate and a plurality of spacers on sidewalls of the polysilicon gate are formed. A silicon thin film is deposited on the polysilicon gate to extend a top area thereof. The hydrogen treatment and the deposition of the silicon thin film are accomplished repeatedly, and then a cobalt layer is deposited on the silicon thin film. A portion of the cobalt layer is converted to a CoSi | 07-02-2015 |