Patent application number | Description | Published |
20140178747 | COMPOSITE ELECTRODE MATERIAL OF LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY - A composite electrode material of a lithium secondary battery and a lithium secondary battery are provided. The composite electrode material of the lithium secondary battery at least includes an electrode active powder and a nanoscale coating layer coated on the surface of the electrode active powder, wherein the nanoscale coating layer is composed of a metastable state polymer, a compound A, a compound B, or a combination thereof. The compound A is a monomer having a reactive terminal functional group, and the compound B is a heterocyclic amino aromatic derivative used as an initiator. The weight ratio of the nanoscale coating layer to the composite electrode material of the lithium secondary battery is 0.005% to 10%. | 06-26-2014 |
20150243939 | CAP ASSEMBLY FOR BATTERY - A cap assembly for a battery includes a roll combination member, a terminal combination member, an electrode terminal, a strength reinforcing block, a cap, and a pad assembly. The roll combination member includes at least one opening, so that terminal disposed portions of 2k rolls are capable of passing through the opening and k is an integer greater than 1, wherein one terminal disposed portion is formed by bending portions of central members of two adjacent rolls. The terminal combination member, the electrode terminal, the strength reinforcing block, the cap, and the pad assembly are sequentially combined on the roll combination member, wherein the electrode terminal includes an electrically conductive portion and a thermally conductive portion which surrounds the electrically conductive portion. The cap assembly is electrically connected to the bending portions at the same side of the 2k rolls. | 08-27-2015 |
Patent application number | Description | Published |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20150187591 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 07-02-2015 |
20160064248 | DOUBLE PATTERNING METHOD - In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines. | 03-03-2016 |
Patent application number | Description | Published |
20150090529 | ESCAPE DEVICE AND USE METHOD THEREOF - The present invention relates to an escape device, involving a tube, a rail member, and a sliding unit. The tube, extending along a longitudinal direction, is provided with an exit end and intermittently with a plurality of escape openings. The rail member includes a plurality of sliding tracks sequentially connected to one another, wherein the neighboring sliding tracks are connected to each other by associating a relatively wide first end with a relatively narrow second end, the second end facing the exit end of the tube. The sliding unit comprises a deformable member which is adapted to slide on the rail member and configured to be pressed against by the second ends of the sliding tracks such that a slide resistance is generated to reduce sliding velocity. Therefore, the effects for the reduction of descending velocity as well as rapid and safe escape are achieved. | 04-02-2015 |
20150366439 | METHOD OF OPERATING AN ENDOSCOPE BY CHANGING MAGNETIC FIELD AND CONTROLLING FEEDING AND ROTATION OF THE ENDOSCOPE SYNCHRONOUSLY - A method of operating an endoscope by changing a magnetic field and controlling a feeding and a rotation synchronously comprises steps of: providing an endoscope, the endoscope including a magnetic section formed on a front end thereof, the magnetic section having a multi-section bending portion and a magnetic element; and setting a target position in a space. The method of operating the endoscope further comprises steps of: exerting a magnetic field on the magnetic element of the magnetic section, any one of a size, a direction, and a position of the magnetic field is allowed to be changed after exerting the magnetic field on the magnetic element of the magnetic section so that the magnetic element is guided by the magnetic field; and controlling the endoscope to feed or/and rotate based on the target position and a bendable direction of the multi-section bending portion. | 12-24-2015 |
Patent application number | Description | Published |
20140177908 | SYSTEM OF OBJECT DETECTION - In a system of object detection, a color detector detects at least one image region in an input image having a color specifically pertinent to the object under detection, thereby obtaining an object width. A dynamic down-sampling unit adaptively performs down-sampling on the detected image region using a generated down-sampling factor according to the object width. An image feature generator receives the down-sampled image and accordingly generates image features for describing the object under detection, and a cascade of classifiers then operates on the image features. | 06-26-2014 |
20140177927 | SYSTEM OF IMAGE STEREO MATCHING - A system of image stereo matching includes at least one stereo matching unit (SMU) each receives a first view and a second view of a view pair, according to which the SMU generates a first depth map for the first view. The system also includes a backward tracer operable to receive the first depth map, according to which a second depth map for the second view is derived. | 06-26-2014 |
20160085312 | GESTURE RECOGNITION SYSTEM - A gesture recognition system includes a candidate node detection unit coupled to receive an input image in order to generate a candidate node; a posture recognition unit configured to recognize a posture according to the candidate node; a multiple hands tracking unit configured to track multiple hands by pairing between successive input images; and a gesture recognition unit configured to obtain motion accumulation amount according to tracking paths from the multiple hands tracking unit, thereby recognizing a gesture. | 03-24-2016 |
20160104272 | AUTO-CONTRAST ENHANCEMENT SYSTEM - An auto-contrast enhancement system includes a human visual system (HVS)-based local difference (LD) histogram unit configured to build a LD histogram with respect to intensity values; a histogram classifier configured to categorize histograms of input images based on distribution properties; and a histogram equalization (HE) unit configured to process the input image according to a result of the HVS-based LD histogram unit and the enhancement level determined in the histogram classifier. | 04-14-2016 |
Patent application number | Description | Published |
20140252559 | Multiple Edge Enabled Patterning - Provided is an alignment mark having a plurality of sub-resolution elements. The sub-resolution elements each have a dimension that is less than a minimum resolution that can be detected by an alignment signal used in an alignment process. Also provided is a semiconductor wafer having first, second, and third patterns formed thereon. The first and second patterns extend in a first direction, and the third pattern extend in a second direction perpendicular to the first direction. The second pattern is separated from the first pattern by a first distance measured in the second direction. The third pattern is separated from the first pattern by a second distance measured in the first direction. The third pattern is separated from the second pattern by a third distance measured in the first direction. The first distance is approximately equal to the third distance. The second distance is less than twice the first distance. | 09-11-2014 |
20140256107 | High Gate Density Devices and Methods - A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures. After forming the plurality of epitaxial growth regions, one of the dummy gate structures is removed to form an isolation trench, which is filled with a dielectric layer to form an isolation feature. The remaining dummy gate structures are removed to form gate trenches, and gate structures are formed in the gate trenches. | 09-11-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140367785 | Method of Fabricating a FinFET Device - A semiconductor device includes a substrate and a plurality of fin structures. A first fin structure and a second fin structure are spaced at a distance D | 12-18-2014 |
20150147867 | Method Of Making a FinFET Device - A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. A plurality of mandrel features are formed on a substrate. First spacers are formed along sidewalls of the mandrel feature and second spacers are along sidewalls of the first spacers. Two back-to-back adjacent second spacers separate by a gap in a first region and merge together in a second region of the substrate. A dielectric feature is formed in the gap and a dielectric mesa is formed in a third region of the substrate. A first subset of the first spacer is removed in a first cut. Fins and trenches are formed by etching the substrate using the first spacer and the dielectric feature as an etch mask. | 05-28-2015 |
20150179435 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 06-25-2015 |
20150270129 | PATTERNING METHOD FOR SEMICONDUCTOR DEVICE FABRICATION - A method includes forming a first pattern having a first feature of a first material on a semiconductor substrate. A second pattern with a second feature and third feature of a second material, interposed by the first feature, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the first feature, the second feature, and the third feature. After forming the spacer elements, the second material comprising the second and third features is selectively removed to form a first opening and a second opening. The first feature, the first opening and the second opening are used as a masking element to etch the target layer. | 09-24-2015 |
20150287635 | METHOD OF PATTERNING A FEATURE OF A SEMICONDUCTOR DEVICE - A method including forming a trench over a layer disposed on a semiconductor substrate. The trench is filled with a first material to form a filled trench. A feature of a second material is formed over the filled trench. The feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer. The feature is then planarized to expose a top surface of the filled trench and provide a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench. The first and second portions of the feature are used to define a dimension of an interconnect feature disposed over the semiconductor substrate. | 10-08-2015 |
20150311086 | Systems and Methods for a Sequential Spacer Scheme - The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features. | 10-29-2015 |
20150318209 | Self-Aligned Semiconductor Fabrication With Fosse Features - The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer. | 11-05-2015 |
20150380261 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. | 12-31-2015 |
20160005614 | Spacer Etching Process for Integrated Circuit Design - A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. | 01-07-2016 |
20160005617 | METHOD FOR INTEGRATED CIRCUIT PATTERNING - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 01-07-2016 |
Patent application number | Description | Published |
20160049397 | TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers. | 02-18-2016 |
20160049480 | TRANSISTOR, INTEGRATED CIRCUIT AND METHOD OF FABRICATING THE SAME - A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises a single implanted silicide layer or a multiple conductive layers with the implanted silicide layer. | 02-18-2016 |
Patent application number | Description | Published |
20140106160 | ANISOTROPIC CONDUCTIVE FILM AND METHOD FOR MANUFACTURING THE SAME - An anisotropic conductive film includes a base board and an insulation adhesive layer coated on a side surface of the base board. The insulation adhesive layer includes a plurality of conductive particles dispersed in the insulation adhesive layer. Each of the plurality of conductive particles includes a spherical base portion, a conductive film formed on the spherical base portion, and an insulation layer with ceramic materials formed on the conductive film. When the conductive particle is being pressed, the insulation layer is capable of being peeled to partly expose the conductive layer. A method for manufacturing the anisotropic conductive film is also provided. | 04-17-2014 |
20140163177 | PRESSURE SENSITIVE ADHESIVE AND METHOD OF SYNTHESIZING POLYMER USED FOR THE SAME - A method of synthesizing an acrylic polymer used for a pressure sensitive adhesive includes steps as follows: polymerizing one or more acrylic monomers in the presence of a first initiator to obtain an acrylic prepolymer; and polymerizing the acrylic prepolymer and one or more silane coupling agents in the presence of a second initiator to obtain the acrylic polymer. | 06-12-2014 |
20140178603 | ADHESIVE TAPE MAKING METHOD AND EQUIPMENT USED IN THE SAME - An adhesive tape making equipment, includes a coating roll, a spraying member, and a plurality of transporting rolls. A first adhesive is coated on the coating roll. A second adhesive is placed in the spraying member. An adhesive force of the first adhesive is higher than an adhesive force of the second adhesive. The coating roll and the spraying member are located between the plurality of transporting rolls. A method of making the adhesive tape is further provided. | 06-26-2014 |
20140186528 | MASKING METHOD USED IN SURFACE TREATMENT PROCESS - A masking method used in a surface treating process is disclosed. The masking method includes the following steps: preparing paint, coating the paint on inner surfaces of a hole in a workpiece, and curing the paint, thereby forming a protection coating layer on the inner surfaces of the hole to protect the inner surfaces of the hole during a surface treatment process. The paint is resistant to the surface treatment process, and includes resin and solvent. A surface tension of the paint is smaller than or equal to 22 mN/m. | 07-03-2014 |
20140186534 | MASKING METHOD USED IN SURFACE TREATING PROCESS - A masking method for a surface treating process provides an injector filled with infilling material and injecting the infilling material in holes having any shape or size or irregularity in a workpiece. The infilling material is cured to form a protective plug in the hole. The infilling material includes resin resistant to the surface treating process. The infilling material overfills the hole and partly protrudes out from the hole. The protective plug adheres to every inner surface of the hole to protect the inner surfaces of the hole from the surface treating process. Gripping and pulling on the partial protrusion of the protective plugs, that are formed from the cured resin, from the hole elastically reduces the original girth or diameter of the infilling material in the hole to allow easier physical removal. | 07-03-2014 |
20140377532 | ADHESIVE TAPE - An adhesive tape is disclosed. The adhesive tape includes a protective layer, an adhesive layer formed on the protective layer, and a plurality of bearing particles dispersed in the adhesive layer. The bearing particles are hollow and elastic. An impact resistance of the adhesive tape is improved, and an adhering performance is improved. | 12-25-2014 |
20140377536 | ADHESIVE TAPE - An adhesive tape is disclosed. The adhesive tape includes a protective layer, an adhesive layer formed on the protective layer, and a plurality of bearing particles dispersed in the adhesive layer. The bearing particle is hollow, and includes an elastic shell and a filling body received in the elastic shell. The elastic shell defines a plurality of through holes. The filling body is adhesive. An impact resistance of the adhesive tape is improved, and an adhering performance is improved. | 12-25-2014 |
20150187453 | ANISOTROPIC CONDUCTIVE FILM AND METHOD FOR MANUFACTURING THE SAME - An anisotropic conductive film includes a base board and an insulation adhesive layer coated on a side surface of the base board. The insulation adhesive layer includes a plurality of conductive particles dispersed in the insulation adhesive layer. Each of the plurality of conductive particles includes a spherical base portion, a conductive film formed on the spherical base portion, and an insulation layer with ceramic materials formed on the conductive film. The insulation layer defines a plurality of holes, thus the insulation layer is porous, the insulation layer is capable of being partly exposed from the plurality of holes when the plurality of conductive particles is pressed. A method for manufacturing the anisotropic conductive film is also provided. | 07-02-2015 |
20150213738 | LABEL - A label includes a protective layer, an adhesive layer formed on the protective layer, and a number of bearing particles dispersed in the adhesive layer. Each resisting particle includes an elastic shell filled with adhesive. The shell defines a number of through holes. The adhesive can flow into the adhesive layer via the through holes under stress. | 07-30-2015 |
Patent application number | Description | Published |
20140169272 | DEVICE, METHOD AND SYSTEM FOR COMMUNICATING DATA - A device, method and system for communicating data are disclosed. The method for communicating data is adapted for a base station, and the method includes grouping a data for transmission in a plurality of data subsets, in which the data for transmission includes a plurality of information bits, encoding the data subsets; modulating the data subsets, and transmitting the data subsets to a receiving device. A base station includes a communication protocol module grouping a data for transmission in a plurality of data subsets, in which the data for transmission comprises a plurality of information bits, encoding the data subsets, modulating the data subsets, and transmitting the data subsets to a receiving device. | 06-19-2014 |
20150124741 | METHOD OF RADIO COVERAGE EXTENSION AND BASE STATION USING THE SAME - The present disclosure is directed to a method of radio coverage extension and a base station using the same method. According to one of the exemplary embodiments, the base station transmits system information in a radio frame through a broadcast channel and selects a payload structure of repetitive system information from a plurality of predefined payload structures that includes the first payload structure and a second payload structure. The size of first payload structure is greater than the size of second payload structure. The base station transmits within the same radio frame a plurality of the repetitive system information having the payload structure through the broadcast channel in response to transmitting the system information. If the first payload structure mode is selected, there are N1 repetitive system information. If the second payload structure is selected, there are N2 repetitive system information where N2 is smaller than or equal to N1. | 05-07-2015 |
Patent application number | Description | Published |
20120141135 | Optical Communication System, Device and Method Employing Advanced Coding and High Modulation Order - A transmitting device, a receiving device, an optical communication system, and associated methods are provided. The transmitting device transmits an optical signal containing data, and comprises: an optical tone generator for generating at least one optical tone; at least one encoder for performing advanced coding on at least one data signal respectively, each of the at least one data signal carrying a part of the data; at least one mapper for performing high order modulation on the at least one coded data signal; and an up-converter for up-converting the at least one high-order-modulated data signal into the optical signal to be outputted through the at least optical tone. Thereby, high speed (e.g., over 1-Tb/s) transmission per single channel over a long-haul distance (e.g. over 1000-km) with error-free recovery may be achieved. | 06-07-2012 |
20120141138 | System, Devices and Methods for Subcarrier Recovery at Local Oscillator Frequency in Optical OFDM System - The invention provides methods, devices and a system for recovering the corrupted subcarrier at the local oscillator (LO) frequency in coherent optical OFDM transmission. The method includes performing advanced coding on a data signal to obtain an encoded signal; performing high order modulation on the encoded signal to obtain a high-order-modulated signal; performing OFDM modulation on the high-order-modulated signal to obtain an electrical OFDM signal; and performing up-conversion on the electrical OFDM signal to obtain an optical OFDM signal to be output. The inventive technique of employing advanced coding with low rate combining with higher order modulation can be used to reduce the decoding bit error ratio (bit error rate) level, so that the LO subcarrier can be fully recovered while the bandwidth of the transmitted signal may be substantially the same as the existing optical OFDM system, and there is no need to add any feedback control module or feedback loop support or the like to the existing optical OFDM system, so that the complexity of the receiving side can be reduced. | 06-07-2012 |
20130195459 | METHOD AND APPARATUS FOR FIBER NON-LINEARITY MITIGATION | 08-01-2013 |
Patent application number | Description | Published |
20140131760 | LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF - A flip-chip LED including a light emitting structure, a first dielectric layer, a first metal layer, a second metal layer, and a second dielectric layer is provided. The light emitting structure includes a first conductive layer, an active layer, and a second conductive layer. The active layer is disposed on the first conductive layer, and the second conductive layer is disposed on the active layer. The first metal layer is disposed on the light emitting structure and is contact with the first conductive layer, and part of the first metal layer is disposed on the first dielectric layer. The second metal layer is disposed on the light emitting structure and is in contact with the second conductive layer, and part of the second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer. The first conductive layer includes a rough surface so as to improve a light extraction efficiency. | 05-15-2014 |
20140186979 | LIGHT EMITTING DEVICE AND MANUFACTURE METHOD THEREOF - The present disclosure provides a method for forming a light-emitting apparatus, comprising providing a first board having a plurality of first metal contacts, providing a substrate, forming a plurality of light-emitting stacks and trenches on the substrate, wherein the light-emitting stacks are apart from each other by the plurality of the trenches, bonding the light-emitting stacks to the first board, forming an encapsulating material commonly on the plurality of the light-emitting stacks, and cutting the first board and the encapsulating material to form a plurality of chip-scale LED units. | 07-03-2014 |
20150295154 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present disclosure provides a method for forming a light-emitting apparatus, comprising providing a carrier having a plurality of first metal contacts; forming a light-emitting structure comprising a substrate, a first cladding layer on the substrate, an active layer on the first cladding layer, and a second cladding layer on the active layer; bonding the light-emitting structure to the carrier; forming a cap layer on a side of the light-emitting structure opposite to the carrier; and cutting the carrier and the cap layer to form a chip-scale LED unit. | 10-15-2015 |