Patent application number | Description | Published |
20120170616 | Apparatus and Method for Sensing Temperature - An apparatus and a method for sensing temperature are provided. The apparatus includes a first oscillation circuit, a pulse width generator, and a comparison circuit. The first oscillation circuit is for generating a first signal having a first frequency which is related to a to-be-sensed temperature. The pulse width generator is for generating a pulse width signal, the pulse width signal having a pulse width related to the to-be-sensed temperature. The comparison circuit is for generating an output signal indicative of the value of the to-be-sensed temperature according to the first signal and the pulse width signal. | 07-05-2012 |
20130124905 | SENSE AMPLIFIER AND METHOD FOR DETERMINING VALUES OF VOLTAGES ON BIT-LINE PAIR - A sense amplifier and a method for determining the values of the voltages on a bit-line pair are provided. The sense amplifier comprises a first delay chain and a second delay chain. The first delay chain is electrically connected to a bit line and configured for receiving a clock signal and a first voltage on the bit line, so as to delay the clock signal according to the first voltage and to generate a first delay signal accordingly. The second delay chain is electrically connected to a complementary bit line and configured for receiving the clock signal and a second voltage on the complementary bit line, so as to delay the clock signal according to the second voltage and to generate a second delay signal accordingly. | 05-16-2013 |
20130170309 | SENSE-AMPLIFIER CIRCUIT OF MEMORY AND CALIBRATING METHOD THEREOF - A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided. | 07-04-2013 |
20130182519 | MEMORY DEVICE AND VOLTAGE INTERPRETING METHOD FOR READ BIT LINE - A memory device comprises a memory cell array, a first and a second pre-charging switch circuits, a selecting circuit, an auxiliary memory cell array, a dynamic voltage controller and a sense amplifier. The auxiliary memory cell array comprises an auxiliary read bit line and a plurality of memory cells arranged in a column and electrically connected to the auxiliary read bit line. The second pre-charging switch circuit determines whether or not to supply a reference voltage to each of the aforementioned memory cells according to a pre-charging control signal. The dynamic voltage controller determines whether or not to supply a voltage to the auxiliary read bit line according to the voltage level of the output signal of the selecting circuit. The sense amplifier compares the voltage levels of the output signal of the selecting circuit and the voltage on the auxiliary read bit line to output a sensing result accordingly. | 07-18-2013 |
20140023113 | TEMPERATURE SENSOR - A temperature sensor includes a signal delaying apparatus, a comparison apparatus, a multiplier and a counting apparatus. The signal delaying apparatus is configured to receive a step signal, perform a phase delay operation on the received step signal according to a temperature degree, and thereby forming a first output signal. The comparison apparatus is configured to receive the first output signal and the step signal, and accordingly output a second output signal. The multiplier is configured to receive the second output signal and a clock signal, and accordingly output a third output signal. The counting apparatus is configured to receive the third output signal, count the number of pulses of the third output signal, and generate a digital code accordingly. | 01-23-2014 |
20140035550 | VOLTAGE REGULATOR CIRCUIT - A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage. | 02-06-2014 |
20140036959 | TEMPERATURE SENSOR - A temperature sensor includes two signal delaying apparatuses having the same internal circuit structure, a comparison apparatus, a multiplier, and a counting apparatus. One signal delaying apparatus is for delaying the phase of a step signal according to a temperature degree so as to form a first output signal. The other signal delaying apparatus operates at ZTC point and is for delaying the phase of the step signal so as to form a second output signal. The comparison apparatus receives the first and second output signals so as to output a third output signal accordingly. The multiplier receives the third output signal and a clock signal so as to output a fourth output signal accordingly. The counting apparatus is for counting the number of the pulses of the fourth output signal so as to generate a digital code accordingly. | 02-06-2014 |
20140146610 | MEMORY AND OPERATION METHOD THEREOF - An operation method of a memory includes the following steps: determining the number of memory units required to update the content stored therein when the memory is performing a program operation based on the N-bit input data and accordingly generate a first determination result; and providing (N−M) number of loads to a source line decoder of the memory if the first determination result indicates that there are M number of memory units required to update the content stored therein, and thereby coupling the (N−M) number of the provided loads to a transmission path of a power supply voltage in parallel, wherein N and M are natural numbers. A memory is also provided. | 05-29-2014 |
20140300385 | METHOD AND DEVICE FOR PULSE WIDTH ESTIMATION - A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided. | 10-09-2014 |
20140376316 | PROGRAMMABLE MEMORY CELL AND DATA READ METHOD THEREOF - A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided. | 12-25-2014 |
Patent application number | Description | Published |
20140104962 | MEMORY, SUPPLY VOLTAGE GENERATION CIRCUIT, AND OPERATION METHOD OF A SUPPLY VOLTAGE GENERATION CIRCUIT USED FOR A MEMORY ARRAY - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 04-17-2014 |
20140204686 | OPERATION METHOD OF A SUPPLY VOLTAGE GENERATION CIRCUIT USED FOR A MEMORY ARRAY - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of memory array processed by a program operation according to input data, and the comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 07-24-2014 |
20140211573 | MEMORY FOR A VOLTAGE REGULATOR CIRCUIT - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 07-31-2014 |