Patent application number | Description | Published |
20120127872 | SCALABLE VIDEO MULTICAST METHOD IN WiMAX NETWORKS - A scalable video multicast method in WiMAX networks is provided in the embodiments of the present invention. The method arranges data transmitting mechanisms and data transmitting rates for a base station and at least a relay station according to network productivity of each bandwidth unit to satisfy the demands of subscriber stations so as to maximize the network productivity within a limited bandwidth. | 05-24-2012 |
20130147605 | LOW POWER WIRELESS SENSING SYSTEM - A low power wireless sensing system includes: a sensing device senses a peripheral environment to generate sensing data; a transmission device, coupled to the sensing device, is connected to an external network through a communication protocol to establish a wireless sensing network; a storage device stores the sensing data or first firmware; and a microprocessing device generates a control signal to control operations of the sensing device, transmission device and storage device according to the sensing data or a RF signal of the external network. The microprocessing device determines to read the first firmware according to the RF signal, so that second firmware built in the microprocessing device is updated and the control signal is adjusted correspondingly. The microprocessing device makes the transmission device enter a sleep state or perform reconnecting according to the RF signal. | 06-13-2013 |
20130148311 | DOUBLE-LAYER PCB OF LOW POWER WIRELESS SENSING SYSTEM AND MANUFACTURING METHOD - The invention discloses a double-layer PCB of a low power wireless sensing system and a manufacturing method thereof. The low power wireless sensing system includes a first layer and a second layer. The first layer comprises a wireless communication module, a power amplifying module, a USB module, a balun module, an antenna module, a low-frequency oscillator and a high-frequency oscillator. According to the double-layer PCB of the low power wireless sensing system and the manufacturing method thereof, a circuit layout can be performed on the double-layer PCB to reduce volume of the PCB. | 06-13-2013 |
Patent application number | Description | Published |
20100052654 | OPTOELECTRONIC MEMORY DEVICE AND METHOD FOR MANUFACTURING AND MEASURING THE SAME - The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer. | 03-04-2010 |
20100072976 | SENSING ELEMENT, MANUFACTURING METHOD THEREOF, AND BIOLOGICAL DETECTION SYSTEM EMPLOYING SUCH SENSING ELEMENT - A sensing element includes a field-effect transistor (FET) with an ultra-thin channel, a reference electrode, a first and a second passivation layer, and a microchannel. The first and the second passivation layer enclose a first and a second portion of the FET, respectively. The microchannel is bonded to the first and the second passivation layer, such that the microchannel is extended across the channel of the ultra-thin channel FET. The ultra-thin channel has a chemically or physically modified surface. When an analyte to be tested passes through the microchannel and is in contact with the modified surface of the ultra-thin channel, it results in changes in the conductance of the ultra-thin channel FET. Trace detection may be conducted on the analyte by observing changes in the conductance. A method for manufacturing the sensing element and a biological detection system employing the sensing element are also provided. | 03-25-2010 |
20100321044 | Sensing element integrating silicon nanowire gated-diodes, manufacturing method and detecting system thereof - The invention disclosed a sensing element integrating silicon nanowire gated-diodes with microfluidic channel, a manufacturing method and a detecting system thereof. The sensing element integrating silicon nanowire gated-diodes with a microfluidic channel comprises a silicon nanowire gated-diode, a plurality of reference electrodes, a passivation layer and a microfluidic channel. The reference electrodes are formed on the silicon nanowire gated-diodes, and the passivation layer having a surface decorated with chemical materials is used for covering the silicon nanowire gated-diodes, and the microfluidic channel is connected with the passivation layer. When a detecting sample is connected or absorbed on the surface of the passivation layer, the sensing element integrating silicon nanowire gated-diodes with the microfluidic channel can detect an electrical signal change. | 12-23-2010 |
20120112756 | OPTOELECTRONIC MEMORY DEVICE AND METHOD FOR MANUFACTURING AND MEASURING THE SAME - The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer. | 05-10-2012 |
20120286768 | METHOD FOR MANUFACTURING OPTOELECTRONIC MEMORY DEVICE - The present invention provides an optoelectronic memory device, the method for manufacturing and evaluating the same. The optoelectronic memory device according to the present invention includes a substrate, an insulation layer, an active layer, source electrode and drain electrode. The substrate includes a gate, and the insulation layer is formed on the substrate. The active layer is formed on the insulation layer, and more particularly, the active layer is formed of a composite material comprising conjugated conductive polymers and quantum dots. Moreover, both of the source and the drain are formed on the insulation layer, and electrically connected to the active layer. | 11-15-2012 |
Patent application number | Description | Published |
20090114151 | Apparatuses and Methods for Maskless Mesoscale Material Deposition - Apparatuses and processes for maskless deposition of electronic and biological materials. The process is capable of direct deposition of features with linewidths varying from the micron range up to a fraction of a millimeter, and may be used to deposit features on substrates with damage thresholds near 100° C. Deposition and subsequent processing may be carried out under ambient conditions, eliminating the need for a vacuum atmosphere. The process may also be performed in an inert gas environment. Deposition of and subsequent laser post processing produces linewidths as low as 1 micron, with sub-micron edge definition. The apparatus nozzle has a large working distance—the orifice to substrate distance may be several millimeters—and direct write onto non-planar surfaces is possible. | 05-07-2009 |
20110129615 | Apparatuses and Methods for Maskless Mesoscale Material Deposition - Apparatuses and processes for maskless deposition of electronic and biological materials. The process is capable of direct deposition of features with linewidths varying from the micron range up to a fraction of a millimeter, and may be used to deposit features on substrates with damage thresholds near 100° C. Deposition and subsequent processing may be carried out under ambient conditions, eliminating the need for a vacuum atmosphere. The process may also be performed in an inert gas environment. Deposition of and subsequent laser post processing produces linewidths as low as 1 micron, with sub-micron edge definition. The apparatus nozzle has a large working distance—the orifice to substrate distance may be several millimeters—and direct write onto non-planar surfaces is possible. | 06-02-2011 |
20130260056 | Apparatuses and Methods for Maskless Mesoscale Material Deposition - Apparatuses and processes for maskless deposition of electronic and biological materials. The process is capable of direct deposition of features with linewidths varying from the micron range up to a fraction of a millimeter, and may be used to deposit features on substrates with damage thresholds near 100° C. Deposition and subsequent processing may be carried out under ambient conditions, eliminating the need for a vacuum atmosphere. The process may also be performed in an inert gas environment. Deposition of and subsequent laser post processing produces linewidths as low as 1 micron, with sub-micron edge definition. The apparatus nozzle has a large working distance—the orifice to substrate distance may be several millimeters—and direct write onto non-planar surfaces is possible. | 10-03-2013 |
Patent application number | Description | Published |
20100289057 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 11-18-2010 |
20130084680 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD, SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD). | 04-04-2013 |
20140299913 | INTEGRATED CIRCUITS USING GUARD RINGS FOR ESD SYSTEMS, AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type. | 10-09-2014 |
Patent application number | Description | Published |
20080211060 | ANTI-FUSE WHICH WILL NOT GENERATE A NON-LINEAR CURRENT AFTER BEING BLOWN AND OTP MEMORY CELL UTILIZING THE ANTI-FUSE - An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly. | 09-04-2008 |
20090026576 | ANTI-FUSE - An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions. | 01-29-2009 |
20090029541 | METHOD OF FABRICATING ANTI-FUSE AND METHOD OF PROGRAMMING ANTI-FUSE - A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer. | 01-29-2009 |
Patent application number | Description | Published |
20120216155 | CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT - A method for checking mask design of an integrated circuit, wherein the integrated circuit includes a plurality of functional elements arranged at different positions, the method includes generating implant layer data of each functional element of the integrated circuit according to characteristics of each functional element; generating mask design data of the integrated circuit according to circuit design of the integrated circuit; generating a block diagram of the integrated circuit according to the mask design data; determining a corresponding position of the functional element in the block diagram according to the implant layer data; and comparing the implant layer data of the functional element with the mask design data at the corresponding position. | 08-23-2012 |
20130009232 | NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate. | 01-10-2013 |
20130026557 | SONOS NON-VOLATILE MEMORY CELL AND FABRICATING METHOD THEREOF - A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening. | 01-31-2013 |
20130043513 | SHALLOW TRENCH ISOLATION STRUCTURE AND FABRICATING METHOD THEREOF - A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure. | 02-21-2013 |
20140073109 | FABRICATING METHOD OF SHALLOW TRENCH ISOLATION STRUCTURE - A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure. | 03-13-2014 |