Patent application number | Description | Published |
20090206909 | BIDIRECTIONAL CONTROLLING DEVICE FOR INCREASING RESISTANCE OF ELEMENTS ON VOLTAGE STRESS - A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets. | 08-20-2009 |
20100059758 | PIXEL STRUCTURE OF A DISPLAY PANEL - A tri-gate pixel structure includes three sub-pixel regions, three gate lines, a data line, three thin film transistors (TFTs), three pixel electrodes, and a common line. The gate lines are disposed along a first direction, and the data line is disposed along a second direction. The TFTs are disposed in the sub-pixel regions respectively, wherein each TFT has a gate electrode electrically connected to a corresponding gate line, a source electrode electrically connected to the data line, and a drain electrode. The three pixel electrodes are disposed in the three sub-pixel regions respectively, and each pixel electrode is electrically connected to the drain electrode of one TFT respectively. The common line crosses the gate lines and partially overlaps the three gate lines, and the common line and the three pixel electrodes are partially overlapped to respectively form three storage capacitors. | 03-11-2010 |
20100225570 | LIQUID CRYSTAL DEVICE WITH MULTI-DOT INVERSION - An LCD device includes a plurality of data lines, a plurality gate lines, a pixel matrix, and a source driver. The pixel matrix includes an mth pixel column and an (m+1)th pixel column. The odd-numbered pixels of the mth pixel column are coupled to an mth data line and corresponding odd-numbered gate lines. The even-numbered pixels of the mth pixel column is coupled to an (m+1)th data line and corresponding even-numbered gate lines. The odd-numbered pixels of the (m+1)th pixel column is coupled to the (m+1)th data line and corresponding odd-numbered gate lines. The even-numbered pixels of the (m+1)th pixel column is coupled to an (m+2)th data line and corresponding even-numbered gate lines. The gate driver outputs the data driving signals having a first polarity to the odd-numbered data lines, and outputs the data driving signals having a second polarity to the even-numbered data lines. | 09-09-2010 |
20100238143 | HIGH-RELIABILITY GATE DRIVING CIRCUIT - A high-reliability gate driving circuit includes a plurality of odd shift register stages and a plurality of even shift register stages. Each odd shift register stage generates a corresponding gate signal furnished to a corresponding odd gate line according to a first clock and a second clock having a phase opposite to the first clock, and further functions to pull down a gate signal of at least one even gate line or at least one odd gate line different from the corresponding odd gate line. Each even shift register stage generates a corresponding gate signal furnished to a corresponding even gate line according to a third clock and a fourth clock having a phase opposite to the third clock, and further functions to pull down a gate signal of at least one odd gate line or at least one even gate line different from the corresponding even gate line. | 09-23-2010 |
20100295764 | DISPLAY DEVICE - A display device includes a substrate, gate lines, data lines, data signal links, and contact vias. The substrate includes a display region, and a peripheral region surrounding the display region. The gate lines, data lines, data signal links, and contact vias are disposed within the display region of the substrate. The gate lines cross the data lines. Each of the data signal links is disposed between adjacent gate lines. Each of the contact vias is disposed between each of the data signal links and a corresponding data line, such that each of the data signal links is electrically connected with the corresponding data line. | 11-25-2010 |
20100315317 | DISPLAY DEVICE - A display device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first signal internal links. The first signal lines and the second signal lines are crossed and disposed in a display region of the substrate. The first signal internal links are disposed in the display region of the substrate, wherein each of the first signal internal links is electrically connected to a corresponding first signal line and disposed between two adjacent second signal lines. Each of the first signal internal links intersects the first signal lines, and the number of intersection points of each of the first signal internal links and the first signal lines is the same. | 12-16-2010 |
20110080384 | Flat Panel Display with Circuit Protection Structure - A flat panel display with a circuit protection structure is provided. The flat panel display includes a substrate, an electrode array control circuit, a driving circuit, a display panel, and a protection unit. The substrate has a first surface. The electrode array control circuit is formed on the first surface. The driving circuit is formed on the first surface and on one side of the electrode array control circuit. The display panel including a plurality of display particles is disposed on the electrode array control circuit. The electrode array control circuit controls operations of the display particles. The protection unit is formed on one side of the display panel to cover the driving circuit. | 04-07-2011 |
20110279491 | DRIVING METHOD OF BISTABLE DISPLAY DEVICE - An exemplary driving method is adapted for a bistable display device including a pixel array. The pixel array includes a plurality of first pixels and a plurality of second pixels arranged in a predetermined manner. The driving method includes the following steps of: during a first time period, providing the first pixels with a first pixel voltage for black insertion and providing the second pixels with a second pixel voltage different from the first pixel voltage; during a second time period following the first time period, providing the first pixels with the second pixel voltage for white insertion and maintaining the second pixels provided with the second pixel voltage for white insertion; and during a third time period following the second time period, initiating the first pixels to display a gray scale image and providing the second pixels with the first pixel voltage for black insertion. | 11-17-2011 |
20120133392 | MULTIPLEX GATE DRIVING CIRCUIT - A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel. | 05-31-2012 |
20130075766 | THIN FILM TRANSISTOR DEVICE AND PIXEL STRUCTURE AND DRIVING CIRCUIT OF A DISPLAY PANEL - A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device. | 03-28-2013 |