Shen, Hsinchu
An-Xing Shen, Hsinchu TW
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20110278656 | STACKED CAPACITOR FOR DOUBLE-POLY FLASH MEMORY - A stacked capacitor for double-poly flash memory is provided. The stacked capacitor is formed by a lower electrode, a lower dielectric layer, a central electrode, an upper dielectric layer, and an upper electrode, wherein the lower electrode is a doped region in a substrate. The manufacturing process of this stacked capacitor can be fully integrated in to the manufacturing process of the double-poly flash memory cell. | 11-17-2011 |
Benjamin Cheng Yu Shen, Hsinchu TW
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20130112557 | Handheld Blood Glucose Monitoring Device With Messaging Capability - A patient monitoring network pertaining to blood glucose and other analyte measurements includes wireless blood glucose or other analyte measuring devices and a networked computer or server. Each monitoring device is associated with a patient and is configured to measure the glucose level or other analyte from a given blood sample via inserted test strips, transmit the measurements to the networked computer, and display received messages. The blood glucose monitoring device includes means for substantially reducing factors that could affect the glucose measurement such as thermal and RF interference. | 05-09-2013 |
20150285759 | Handheld Blood Glucose Monitoring Device With Messaging Capability - A patient monitoring network pertaining to blood glucose and other analyte measurements includes wireless blood glucose or other analyte measuring devices and a networked computer or server. Each monitoring device is associated with a patient and is configured to measure the glucose level or other analyte from a given blood sample via inserted test strips, transmit the measurements to the networked computer, and display received messages. The blood glucose monitoring device includes means for substantially reducing factors that could affect the glucose measurement such as thermal and RF interference. | 10-08-2015 |
Chang-Han Shen, Hsinchu TW
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20100148702 | LIQUID CRYSTAL DISPLAY AND OVERHEAT PROTECTION METHOD THEREOF - A liquid crystal display equipped with an overheat protection device and overheat protection method is disclosed. When a temperature sensor measures that the temperature of a LED (Light-Emitting Diode) backlight module is overheated and possibly will cause damage, the overheat protection device descend the luminance of the LED backlight module to lower the temperature inside the liquid crystal display. | 06-17-2010 |
20100149081 | DISPLAY SYSTEM AND DRIVING METHOD THEREOF - A display system and driving method thereof are capable of outputting a low luminance of red light, especially through descending a color level of red signals when displayed. The display system includes a display device and an image processing device. The image processing device outputs the red signals to the display device for displaying thereon. The color level of red signals is descended by a display chip or a switch device to allow the display device to display images with low luminance of red light, so that the display device is viewable through a night-vision device. | 06-17-2010 |
20100149743 | PORTABLE ELECTRONIC DEVICE AND CAMERA MODULE THEREOF - A portable electronic device includes a flat display, a transparent window, an optical element, an optical zoom lens set and an image sensing element. The flat display includes a display panel with a viewing direction. The transparent window, the optical element, the optical zoom lens set and the image sensing element are all configure in the outer frame of the flat display. The transparent window and the optical element correspond to each other and align in the viewing direction. The optical zoom lens set includes multiple lenses configured at one side of the optical element. The lenses move along a focusing direction to modify the focusing length. The focusing direction is substantially perpendicular to the viewing direction. The image sensing element is configured at one side of the optical zoom lens set, thereby allowing the light to pass through the transparent window, by the optical element guided to the optical zoom lens set, then passing through the lenses, and finally focusing on the image sensing element, | 06-17-2010 |
20100188341 | DISPLAY DEVICE AND TOUCH MODULE THEREOF - A touch module is provided to be applied to a display device. The touch panel includes a touch panel, a first retarder film, a second retarder film, and a polarizer. The touch panel has a display surface and an embedding surface opposite to each other. The first retarder film is disposed on the display surface, the second retarder film is disposed on the embedding surface, and the polarizer is disposed on the first retarder film. | 07-29-2010 |
Chang Hong Shen, Hsinchu TW
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20100015750 | Process of manufacturing solar cell - A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region. | 01-21-2010 |
20120256181 | POWER-GENERATING MODULE WITH SOLAR CELL AND METHOD FOR FABRICATING THE SAME - The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation. | 10-11-2012 |
20140065754 | METHOD FOR FABRICATING POWER-GENERATING MODULE WITH SOLAR CELL - The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit. | 03-06-2014 |
20140131716 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate. | 05-15-2014 |
20140264271 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots. | 09-18-2014 |
20150280010 | METHOD FOR MANUFACTURING POLYCRYSTALLINE SEMICONDUCTOR THIN FILM AND TRANSISTOR DEVICE STRUCTURE USING THE SAME - A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer. | 10-01-2015 |
Chein-Fu Shen, Hsinchu TW
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20150214196 | MULTI-DIMENSIONAL LIGHT-EMITTING DEVICE - The present application provides a multi-dimensional light-emitting device electrically connected to a power supply system. The multi-dimensional light-emitting device comprises a substrate, a blue light-emitting diode array and one or more phosphor layers. The blue light-emitting diode array, disposed on the substrate, comprises a plurality of blue light-emitting diode chips which are electrically connected. The multi-dimensional light-emitting device comprises a central area and a plurality of peripheral areas, which are arranged around the central area. The phosphor layer covers the central area. When the power supply system provides a high voltage, the central area and the peripheral areas of the multi-dimensional light-emitting device provide a first light and a plurality of second lights, respectively. The first light and the second lights are blended into a mixed light. | 07-30-2015 |
Cheng-Hui Shen, Hsinchu TW
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20100301236 | Shorten Temperature Recovery Time of Low Temperature Ion Implantation - The present invention discloses a low temperature ion implantation by performing a heating process after the end of an implanting process and before the wafer is moved into the external environment. This invention actively raises wafer temperature at a time no later than implementation of the vacuum venting process, such that the condensed moisture induced by the temperature difference between a vacuum environment inside ion implanter and an external environment outside ion implanter is effectively minimized. The wafer can be heated at a loadlock, a robot for transferring wafer and/or an implantation chamber. The wafer can be heated by a gas, a liquid, a light and/or a heater embedded in a holder for holding the wafer. | 12-02-2010 |
Chi Shen, Hsinchu TW
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20130092595 | WAFER CARRIER - A wafer carrier comprises a supporting body having a height and comprising an opening, wherein a bottom surface of the opening is a curved surface; and a plurality of supporting rods formed around a periphery of the supporting body. Another aspect of the present application provides a manufacturing method of the wafer carrier. The method comprises forming an epitaxial layer on a growth substrate to form a wafer structure; measuring a curvature radius of the wafer structure; and providing the wafer carrier described above in accordance with the curvature radius of the wafer structure. | 04-18-2013 |
20140102372 | WAFER CARRIER - A wafer carrier comprises a supporting body having a height and comprising an opening, wherein a bottom surface of the opening is a curved surface; and a plurality of supporting rods formed around a periphery of the supporting body. Another aspect of the present application provides a manufacturing method of the wafer carrier. The method comprises forming an epitaxial layer on a growth substrate to form a wafer structure; measuring a curvature radius of the wafer structure; and providing the wafer carrier described above in accordance with the curvature radius of the wafer structure. | 04-17-2014 |
Chia-Chieh Shen, Hsinchu TW
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20080248366 | FUEL CELL WITH A COMBINED FUEL SUPPLY UNIT AND POWER GENERATING UNIT STRUCTURE - The present invention is a fuel cell with a combined fuel supply unit and power generating unit. The fuel cell includes a fuel supply unit, a power generating unit, and an enclosure. The fuel supply or fuel storage unit is incorporated laterally or internally into the power generating unit, thereby shortening the fuel pipeline. The performance of the fuel cell is improved, and the space required for fuel cell is reduced for greater applicability. | 10-09-2008 |
20120225009 | HYDROGEN STORAGE MATERIAL ANALYZER AND ANALYSIS AND ACTIVATION METHODS - A hydrogen storage material analyzer along with its analysis and activation methods, the hydrogen storage material analyzer including a H | 09-06-2012 |
Chia-Hui Shen, Hsinchu TW
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20130075779 | LIGHT EMITTING DIODE WITH MULTIPLE TRANSPARENT CONDUCTIVE LAYERS AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a first-type semiconductor layer, an active layer, a second-type semiconductor layer and a transparent, electrically conductive layer formed in sequence. The transparent, electrically conductive layer includes a first transparent, electrically conductive layer on the second-type semiconductor layer and a second transparent, electrically conductive layer on the first transparent, electrically conductive layer. Both the first and second transparent, electrically conductive layers are made of indium tin oxide, while the first transparent, electrically conductive layer has a smaller thickness. During formation of the transparent, electrically conductive layer, a mass flow of introduced oxygen gas to the first transparent conductive layer is lower than that to the second transparent conductive layer. | 03-28-2013 |
20130099254 | LIGHT EMITTING DIODE WITH CHAMFERED TOP PERIPHERAL EDGE - A light emitting diode includes a substrate and a light emitting structure. The light emitting structure includes a light outputting surface away from the substrate and a plurality of sidewalls adjoining the light outputting surface. A top peripheral edge interconnecting the light outputting surface and the sidewalls of the light emitting structure is a rounded top peripheral edge or a beveled top peripheral edge. A top surface of the substrate surrounding the light emitting structure is exposed to air and formed with micro-structures. | 04-25-2013 |
20130175498 | LIGHT EMITTING DIODE - A light emitting diode and a light emitting diode (LED) manufacturing method are disclosed. The LED comprises a substrate; a first n-type GaN layer; a second n-type GaN layer; an active layer; and a p-type GaN layer formed on the substrate in sequence; the second n-type GaN layers has a bottom surface interfacing with the first n-type GaN layer, a rim of the bottom surface has a roughened exposed portion, and Ga-N bonds on the bottom surface has an N-face polarity. | 07-11-2013 |
20130270595 | LIGHT EMITTING DIODE DIE AND LIGHT EMITTING DIODE PACKAGE INCORPORATING THE SAME - An LED die comprises a substrate and an epitaxial layer formed thereon. The epitaxial layer comprises a first n-type semiconductor layer, an active layer and a p-type semiconductor layer grown on the substrate in sequence. The LED die defines a receiving recess formed in a center of a top face of the p-type semiconductor layer. The receiving recess extends through the p-type semiconductor layer, the active layer and into the n-type semiconductor layer along a top-to-bottom direction of the epitaxial layer. A pair of p-pads are located at two opposite sides of the p-type semiconductor layer, respectively. A first n-pad is received in the receiving recess and located on the n-type layer. | 10-17-2013 |
20130280835 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP - A method for manufacturing a light emitting diode includes providing an epitaxial wafer having a substrate and an epitaxial layer allocated on the substrate. The epitaxial layer comprises a first semiconductor layer, an active layer, a second semiconductor layer sequentially allocated, and at least one blind hole penetrating the second semiconductor layer, the active layer and inside the first semiconductor layer; then a first electrode is formed on the first semiconductor layer inside the at least one blind hole and a second electrode is formed on the second semiconductor layer; thereafter a first supporting layer is allocated on the first electrode and a second supporting layer is allocated on the second electrode. | 10-24-2013 |
20130309795 | METHOD FOR MANUFACTURING LED CHIP WITH INCLINED SIDE SURFACE - A method for manufacturing an LED chip is disclosed wherein a substrate is provided. A first semi-conductor layer is formed on the substrate. A photoresist layer with an inverted truncated cone shape and a blocking layer with an inclined inner surface facing and surrounding the photoresist layer are formed on the first semi-conductor layer. The photoresist layer is removed and an epitaxial region surrounded by the blocking layer is defined. A lighting structure is formed inside the epitaxial region. The blocking layer is then removed and the first semi-conductor layer is exposed. Electrodes are formed and respectively electrically connected to the first semi-conductor layer and the lighting structure. | 11-21-2013 |
20140138615 | LIGHT EMITTING DIODE - An LED includes a base and an LED die grown on the base. The LED die includes two spaced electrodes and two exposed semiconductor layers. The two electrodes are respectively formed on top surfaces of the two semiconductor layers. At least one of the electrodes extends downwardly from the top surface of the corresponding semiconductor layer along a lateral edge of the LED die to electrically connect an exterior electrode via transparent conducting resin. | 05-22-2014 |
Chien Fu Shen, Hsinchu JP
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20120286317 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack includes: a first semiconductor layer; an active layer formed on the first semiconductor layer; and a second semiconductor layer formed on the active layer; a recess structure formed through the second semiconductor layer, the active layer, and extended in the first semiconductor layer, wherein the first semiconductor layer includes a contact region defined by the recess structure; a first electrode structure including a first contact portion on the contact region of the first semiconductor layer, and a second contact portion laterally extended from the first contact portion into the first semiconductor layer; and a dielectric layer formed on side surfaces of the second semiconductor layer and the active layer to insulate the second semiconductor layer and the active layer from the first contact portion. | 11-15-2012 |
Chien-Fu Shen, Hsinchu TW
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20080303047 | Light-emitting diode device and manufacturing method therof - A light-emitting diode (LED) device and manufacturing methods thereof are disclosed, wherein the LED device comprises a substrate, a plurality of micro-lens, a reflector, a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a first electrode and a second electrode. The substrate has a plurality of micro-lens on its upper surface. The first conductivity type semiconductor layer is on the upper surface of the substrate. The active layer and the second conductivity type semiconductor layer are sequentially on a portion of the first conductivity type semiconductor layer. The first electrode is on the other portion of the first conductivity type semiconductor layer uncovered by the active layer. The second electrode is on the second conductivity type semiconductor layer. The reflector layer is on a lower surface of the substrate. | 12-11-2008 |
20090140280 | Light-emitting device - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 06-04-2009 |
20090162960 | Method for manufacturing high efficiency light-emitting diodes - A method for manufacturing a light-emitting device comprising the steps of cutting a light-emitting unit by a laser beam, and cleaning the light-emitting unit by an acid solution to remove by-products resulted from the laser cutting. | 06-25-2009 |
20110089442 | OPTOELECTRONIC DEVICE - An optoelectronic device comprising: a substrate; a plurality of semiconductor units electrically connected with each other and disposed jointly on the substrate, wherein each semiconductor unit comprises a first semiconductor layer, a second semiconductor layer, and an active region interposed between thereof; a plurality of first electrodes disposed on each first semiconductor layer respectively; and a plurality of second electrodes disposed on each second semiconductor layer respectively, wherein at least one of the first electrodes comprises a first extension, and at least one of the second electrodes comprises a second extension, wherein at least one of the first extension and the second extension comprises a curve which is not parallel to the edge of the semiconductor units. | 04-21-2011 |
20110227120 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a substrate, an epitaxial structure formed on the substrate including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer. A trench is formed in the epitaxial structure to expose a part of side surface of the epitaxial structure and a part of surface of the first semiconductor layer, so that a first conductive structure is formed on the part of surface of the first semiconductor layer in the trench, and a second conductive structure is formed on the second semiconductor layer. The first conductive structure includes a first electrode and a first pad electrically contacted with each other. The second conductive structure includes a second electrode and a second pad electrically contacted with each other. Furthermore, the area of at least one of the first pad and the second pad is between 1.5×10 | 09-22-2011 |
20110241057 | HIGH-EFFICIENCY LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device includes a substrate; a first semiconductor layer formed on the substrate; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; and a first pad formed on the second semiconductor layer, wherein the second semiconductor layer includes a plurality of voids between the active layer and the first pad. | 10-06-2011 |
20110281383 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method for manufacturing a light-emitting device comprising the steps of: providing a substrate comprising a first surface and a second surface; forming a plurality of cutting lines on the substrate by a laser beam; cleaning the substrate by a chemical solution; and forming a light-emitting stack on an first surface of the substrate after cleaning the substrate. | 11-17-2011 |
20120211794 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a light-emitting stack having an upper surface and a lower surface; a pad, arranged on the upper surface, comprising: a first bonding region; and a second bonding region physically connected to the first bonding region through a connecting region having a connecting width; a first electrode connected to the first bonding region; a second electrode connected to the second bonding region; and a third electrode extending from the pad and arranged between the first electrode and the second electrode. At least one of the first electrode, the second electrode, and the third electrode has a width smaller than the connecting width. | 08-23-2012 |
20130011949 | METHOD FOR MANUFACTURING HIGH EFFICIENCY LIGHT-EMITTING DIODES - A method of manufacturing a light-emitting device comprising the steps of cutting a substrate by a laser beam to form a cavity in the substrate and generate a by-product directly on the substrate by the cutting, and removing the by-product by a chemical solution containing an acid under a predetermined cleaning temperature. | 01-10-2013 |
20130032848 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device comprises a semiconductor stack comprising a first semiconductor layer, an active layer and a second semiconductor layer, a first electrode electrically connecting with the first semiconductor layer, a second electrode electrically connecting with the second semiconductor layer, wherein there is a smallest distance D | 02-07-2013 |
20130113014 | OPTOELECTRONIC DEVICE - The application provides an optoelectronic device structure, comprising a semiconductor stack, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer; a first electrode electrically connecting with the first conductivity type semiconductor layer, and further comprising a first extension electrode; a second electrode electrically connecting with the second conductivity type semiconductor layer; and a plurality of electrical restraint contact areas between the semiconductor stack and the first extension electrode, wherein the plurality of electrical restraint contact areas is distributed in a variable interval. | 05-09-2013 |
20130119429 | LIGHT-EMITTING ELEMENT AND THE MANUFACTURING METHOD THEREOF - A light-emitting element includes a light-emitting stack includes: a first semiconductor layer; an active layer formed on the first semiconductor layer; and a second semiconductor layer formed on the active layer; a recess structure formed through the second semiconductor layer, the active layer, and extended in the first semiconductor layer, wherein the first semiconductor layer includes a contact region defined by the recess structure; a first electrode structure including a first contact portion on the contact region of the first semiconductor layer, and a second contact portion laterally extended from the first contact portion into the first semiconductor layer; and a dielectric layer formed on side surfaces of the second semiconductor layer and the active layer to insulate the second semiconductor layer and the active layer from the first contact portion. | 05-16-2013 |
20140084327 | LIGHT-EMITTING DEVICE - A light-emitting device comprises: a substrate having a first side and a second side opposite to the first side; a light-emitting stack disposed on the first side and emitting a light having a main wavelength of λ nm; wherein the substrate comprises a first surface on the first side, the first surface comprising a first pattern arranged with a first period, the first pattern comprising a second pattern arranged with a second period; and the first period is greater than 6λ, and the second period is smaller than λ nm. | 03-27-2014 |
20140159091 | LIGHT-EMITTING ELEMENT - A light-emitting element comprises: a light-emitting semiconductor stack comprising a first semiconductor layer; a second semiconductor layer on the first semiconductor layer; and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrode on the first semiconductor layer; a first protection layer on the light-emitting semiconductor stack and comprising a first through hole; and a conductive contact layer on the first protection layer and electrically connected to the first electrode through the first through hole. | 06-12-2014 |
20140191277 | LIGHT-EMITTING DEVICE - A light-emitting device comprises: a light-emitting semiconductor stack comprising a recess and a mesa, wherein the recess comprises a bottom and the mesa comprises an upper surface; a first insulating layer in the recess and on a part of the upper surface of the mesa; and a first electrode comprising a first layer and a second layer, wherein the first layer comprises a first conductive material and is on another part of the upper surface of the mesa, and the second layer comprises a second conductive material and is on the first layer. | 07-10-2014 |
20140367733 | LIGHT-EMITTING DEVICE - A light-emitting device comprises: a light-emitting stack having an upper side, a first edge having an end point, and a second edge opposite to the first edge; a first bonding region arranged on the upper side, near the first edge, and far from the end point; a second bonding region separated from to the first bonding region by a first distance and being far from the end point; a third bonding region arranged on the upper side; a fourth bonding region separated from the third bonding region by a second distance longer than the first distance; a first electrode connected to the first bonding region; a second electrode connected to the second bonding region; a third electrode connected to the third bonding region; a fourth electrode connected to the fourth bonding region; and a fifth electrode connected to the first bonding region and pointing to the fourth bonding region. | 12-18-2014 |
20150123152 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a light-emitting stacked layer including an upper surface, wherein the upper surface includes a first flat region; a protective layer including a current blocking region on the first flat region; and a cap region on the upper surface, wherein the current blocking region is spatially separate from the cap region; and a first electrode covering the current blocking region. | 05-07-2015 |
20150255676 | LIGHT-EMITTING ELEMENT - A light-emitting element comprises a light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a plurality of extensions formed on the first semiconductor layer; and a first conductive part and a second conductive part formed on the light-emitting semiconductor stack and respectively electrically connected to the first semiconductor layer and the second semiconductor layer, wherein one of the plurality of extensions is formed beyond a projected area of the second conductive part and not covered by the first conductive part. | 09-10-2015 |
20150357524 | LIGHT-EMITTING ELEMENT - A light-emitting element comprises a light-emitting semiconductor stack comprising a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; a first electrode comprising an contact area and an extension electrically connected to the first semiconductor layer, wherein the extension is connected to the contact area; a second electrode on the second semiconductor layer; and a first conductive part and a second conductive part formed on the light-emitting semiconductor stack and respectively electrically connected to the first electrode and the second electrode, wherein the extension is formed beyond a projected area of the second conductive part and not covered by the first conductive part, and the contact area is covered by the first conductive part. | 12-10-2015 |
20160005926 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device, comprising: a first semiconductor layer comprising four boundaries, a corner formed by two of the neighboring boundaries, a first surface, and a second surface opposite to the first surface; a second semiconductor layer formed on the first surface of the first semiconductor layer; a second conductive type electrode formed on the second semiconductor layer; and two first conductive type electrodes formed on the first surface, wherein the first conductive type electrodes are separated and formed a pattern. | 01-07-2016 |
20160049442 | Light-Emitting Structure - A light-emitting structure, comprising a substrate; a first unit and a second unit, separately formed on the substrate; a trench between the first unit and the second unit; and an electrical connection, electrically connecting the first unit and the second unit and comprising a bridging portion and a joining portion extending from the bridging portion, wherein the bridging portion is wider than the joining portion and the bridging portion is configured to cover the trench, and the joining portion is configured to cover first unit and the second unit. | 02-18-2016 |
Ching-Hsing Shen, Hsinchu TW
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20140159099 | Method of making a light emitting device and light emitting device made thereof - A method of manufacturing a light-emitting device comprises: providing a substrate, forming a light-emitting structure on the substrate, the light-emitting structure having an active layer; forming a protective layer on the light-emitting structure, the protective layer having a first thickness; etching the protective layer such that the protective layer has a second thickness less than the first thickness; and patterning the protective layer. | 06-12-2014 |
20140209949 | LIGHT-EMITTING ELEMENT COMPRISING A REFLECTIVE STRUCTURE WITH HIGH EFFICIENCY - A light-emitting element, comprises: a substrate; a light-emitting semiconductor stack over the substrate and comprising an active layer; and a Distributed Bragg reflective unit under the substrate comprising a first Distributed Bragg reflective structure under the substrate and comprising a first number of pairs of alternately stacked first sub-layers and second sub-layers, and a second Distributed Bragg reflective structure under the first Distributed Bragg reflective structure and comprising a second number of pairs of alternately stacked third sub-layers and fourth sub-layers, wherein the first number is different from the second number. | 07-31-2014 |
Chi-Tsan Shen, Hsinchu TW
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20100277859 | Electronic Apparatus Having Movable Input Device - An electronic apparatus having movable input device includes a main body and two input devices. The main body includes a shell, a display panel and a processing unit. The display panel and the processing unit are received in the shell. A display surface of the display panel is exposed from the shell. The two input devices are coupled to two opposite sides of the shell respectively and electrically connect to the processing unit. The two input devices are configured for being slid or rotated relative to the shell so as to be received by the shell, thereby facilitating to reduce the volume of the electronic apparatus. | 11-04-2010 |
20120307343 | ELECTROPHORETIC DISPLAY - Disclosed herein is an electrophoretic display, which includes a first substrate, an electrophoretic layer, a second substrate, a stress controlling layer and an adhesive layer. The first substrate includes at least one active device and at least one pixel electrode electrically coupled to the active device. The electrophoretic layer is disposed above the pixel electrode. The second substrate is disposed above the electrophoretic layer. The stress controlling layer is formed on a lower surface of the second substrate. The adhesive layer is disposed between the surface stressed layer and the electrophoretic layer, and is in contact with the stress controlling layer and the electrophoretic layer. The adhesion between the stress controlling layer and the adhesive layer is about 75% to 125% of the adhesion between the electrophoretic layer and the adhesive layer. | 12-06-2012 |
20150316828 | ELECTROPHORETIC DISPLAY - Disclosed herein is an electrophoretic display, which includes a first substrate, an electrophoretic layer, a second substrate, a stress controlling layer and an adhesive layer. The first substrate includes at least one active device and at least one pixel electrode electrically coupled to the active device. The electrophoretic layer is disposed above the pixel electrode. The second substrate is disposed above the electrophoretic layer. The stress controlling layer is formed on a lower surface of the second substrate. The adhesive layer is disposed between the surface stressed layer and the electrophoretic layer, and is in contact with the stress controlling layer and the electrophoretic layer. The adhesion between the stress controlling layer and the adhesive layer is about 75% to 125% of the adhesion between the electrophoretic layer and the adhesive layer. | 11-05-2015 |
Chun-Lin Shen, Hsinchu TW
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20110074806 | METHOD FOR EXTENDING DURATION OF A DISPLAY APPARATUS HAVING BRIGHTNESS COMPENSATION AND APPARATUS REALIZING THE SAME - For improving the drawback of brightness decay of a display due to aging, a memory can be used to store the usage time of each pixel of the display, then based upon the usage time the brightness decay of each pixel of the display can be compensated and accordingly the value for the compensation can be stored in a volatile memory and a non-volatile memory. However, the usage of the non-volatile memory is limited. Hence, the present invention discloses a new approach for storing the data so as to decrease write-in sequence per unit area for the non-volatile memory rather than increasing its storing capacity proportionally. | 03-31-2011 |
20110074834 | BRIGHTNESS COMPENSATION APPARATUS AND APPLICATION METHOD THEREOF - For improving the brightness decay of a display due to its aging, a non-volatile memory such as Flash can be used to store a brightness accumulation value of each point of the display, and each point can be compensated for its brightness accordingly. However, the non-volatile memory suffers from incorrect write-in data or temporary power disconnection, and thus the error will exist all the time to make the display non-even. Hence, the present invention uses a multiple data backups and CRC error detection, plus new/old data comparison to protect data the non-volatile memory from incorrect brightness compensation value so as to uniform the brightness of the display. | 03-31-2011 |
Geng-Shin Shen, Hsinchu TW
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20090146278 | Chip-stacked package structure with asymmetrical leadframe - The present invention provides a chip-stacked package structure, comprising: a lead-frame, composed of a plurality of inner leads and a plurality of outer leads, wherein the inner leads comprise a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, and the ends of the first inner leads and the second inner leads are arranged opposite each other at a distance. The first inner leads is provided with a down-set structure, which results in different vertical heights of the position of the end of first inner leads and the position of the end of second inner leads. A chip-stacked package structure is then fixedly connected to the first inner leads, and the metallic bonding pads on the same side edge are electrically connected to the first inner leads and the second inner leads through a plurality of metal wires; and an encapsulant with a top surface and a bottom surface is provided to cover the chip-stacked package structure and the inner leads. | 06-11-2009 |
20110068455 | PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips. | 03-24-2011 |
20110207262 | Method For Manufacturing A Semiconductor Structure - The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps of: forming a substrate having a package array, wherein the package array has a plurality of contact pads and a protection layer, and the plurality of contact pads are exposed to the outer side of the protection layer; forming a thermosetting non-conductive layer covering the substrate; partially solidifying the thermosetting non-conductive layer to form a semi-solid non-conductive layer; connecting chips to the package array on the substrate, wherein each of the chips has an active surface, a plurality of chip pads and a plurality of composite bumps, the chip pads are formed on the active surface, and the composite bumps are formed on the chip pads so that the composite bumps electrically connect to each of the contact pads; pressing and heating the chips and the substrate so that the semi-solid non-conductive layer adheres with the chips and the substrate; pre-heating an encapsulant preformed on a metal layer; covering the chips on the substrate with the encapsulant; and solidifying the encapsulant to completely cover the chips on the substrate. The present invention can reduce use of gold to lower the manufacturing cost and can also improve the heat conduction efficiency of the semiconductor structure to enhance operational stability of the chips. | 08-25-2011 |
20110298124 | Semiconductor Structure - A semiconductor structure is provided. By using a composite bump with replace of a gold bump, the consumption of gold can be reduced and the manufacturing cost can be decreased accordingly. Moreover, by using an encapsulation material formed on a metal layer, the heat transferring efficiency of the semiconductor structure can be improved and the stability thereof can be increased. | 12-08-2011 |
20120018883 | CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT - A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit has a substrate, a plurality of pads and a passivation layer. The pads are disposed on the substrate. The passivation layer extends over and covers a part of the substrate and a part of around each of the pads to define a plurality of openings, in which the conductive structure electrically connects to a corresponding pad of the pads through a corresponding opening of the openings. The conductive structure includes a buffering layer, an under bump metallurgy (UBM) layer and a bump. The buffering layer is formed on the passivation layer without fully blocking the corresponding opening. The UBM layer is substantially formed in the corresponding opening and electrically connects to the corresponding pad. Additionally, the UBM layer, formed under the bump, continuously extends over and covers a peripheral portion of the buffering layer. | 01-26-2012 |
20120074402 | PACKAGING STRUCTURE - This invention relates to a packaging structure and method for manufacturing the packaging structure. The packaging structure comprises a substrate film, a plurality of chips, a compound resin layer and a support layer. The substrate film is formed with circuits having a plurality of terminals exposed from a solder mask. The chips, each of which has a plurality of pads, under bump metals (UBMs) formed on the pads, and composite bumps disposed onto the UBMs, are bonded onto the substrate film to form the first tape. The second tape comprises the support layer and the compound resin layer formed on the support layer. The first tape and the second tape are both in reel-form and are expanded towards a pair of rollers to be heated and pressurized for encapsulating the chips. | 03-29-2012 |
20120278789 | COMPUTER IMPLEMENTED APPARATUS FOR GENERATING AND FILTERING CREATIVE PROPOSAL - A computer implemented apparatus for automatically generating and filtering creative proposals is disclosed. Particularly, the computer implemented apparatus automatically generates all possible featured component code sets which corresponding to all possible featured components, and compares them to the prior art code sets which corresponding to the prior objects. Thereby, the novel code sets which corresponding to the novel creative proposals are rapidly filtered out. The computer implemented apparatus comprises a standard component database, a permutation and combination module, a featured component code set database, a prior art code set database, a matching module, a sifting module and an output module. | 11-01-2012 |
20120313234 | QFN PACKAGE AND MANUFACTURING PROCESS THEREOF - The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided. | 12-13-2012 |
20130127047 | CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer. | 05-23-2013 |
20130147037 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch. | 06-13-2013 |
20130249042 | STRUCTURE OF STACKING CHIPS AND METHOD FOR MANUFACTURING THE SAME - A structure of stacking chips and a method for manufacturing the structure of stacking chips are provided. A wafer with optical chips and a glass substrate with signal processing chips are stacked with each other, and then subjected to ball mounting and die sawing to form the stacked packaging structure. The optical chips and the signal processing chips form the electrical connection on the surface of the glass substrate via the through holes thereof. | 09-26-2013 |
20130280865 | QFN Package and Manufacturing Process Thereof - The present invention provides a Quad Flat Non-leaded (QPN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided. | 10-24-2013 |
20130294033 | THERMALLY ENHANCED ELECTRONIC PACKAGE - A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages. | 11-07-2013 |
Guan-Jie Shen, Hsinchu TW
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20150294874 | DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A T-SHAPE IN THE METAL GATE LINE-END - A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and STI using a dry etch process and a wet lateral etch process to form a T-shape void in the semiconductor device, and depositing metal gate material in the T-shape void to form a T-shape structure in a metal gate line-end. A semiconductor device fabricated from a process that included the removal of a dummy poly gate is disclosed. The semiconductor device comprises an OD fin and a metal gate fabricated above a section of the OD fin and adjacent to a side section of the OD fin. The metal gate has a T-shape structure in a metal gate line-end. The T-shape structure was formed by removing IL oxide and STI using a dry and a wet lateral etch process to form a T-shape void. | 10-15-2015 |
20150332957 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH REDUCED LEAK PATHS - A method of fabricating a semiconductor device with reduced leak paths is disclosed. The method comprises etching a void in non-conductive material in the semiconductor device to provide a conduction path between isolated material, forming a non-conductive surface layer on an unintended conductive item adjacent to the void, and filling the void with a conductive material. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void. Forming a non-conductive surface layer may comprise oxidizing a surface surrounding the void using plasma oxidation operations. Forming a non-conductive surface layer may comprise oxidizing a side wall of the void using plasma oxidation operations. The unintended conductive item may comprise a conductive impurity or conductive residue. The void may comprise a trench or a hole for a via. | 11-19-2015 |
Hsiang Yin Shen, Hsinchu TW
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20120027544 | SYSTEM AND METHOD OF MONITORING AN ENVIRONMENTAL PARAMETER ALONG A PREDETERMINED ROUTE - A monitoring system has a vehicle and a monitoring device. The vehicle is movable along a predetermined route, and the monitoring device is detachably mounted to the vehicle. The vehicle has a photonic device configured to read position information according to detection of a positioning tag positioned at a predetermined position along the predetermined route. The monitoring device has a sensor configured to monitor an environmental parameter and a controller communicatively coupled to the sensor and the photonic device. The controller is configured to record the monitored environmental parameter along the predetermined route and the position information. | 02-02-2012 |
20130230375 | AUTOMATED MATERIAL HANDLING SYSTEM AND METHOD FOR SEMICONDUCTOR MANUFACTURING - A rail transport system and method for a semiconductor fabrication facility (FAB). In one embodiment, the system includes a network of stationary rails and a wheeled vehicle movable on the rails via rolling movement. The vehicle is operable to hold a wafer carrier that stores a plurality of wafers. A cross-floor transport system is provided that may include a vehicle lifter positioned near the network of rails that extends between a first elevation and a second elevation in the FAB. The lifter is configured and operable to receive the vehicle from rails at the first elevation and vertically transport the vehicle to rails at the second elevation without removing the wafer carrier from the wheeled vehicle. In one embodiment, the lifter is configured so that the vehicle may be rolled directly onto and off of the lifter for vertical transport. | 09-05-2013 |
20140075774 | SEMICONDUCTOR APPARATUS WITH INNER WAFER CARRIER BUFFER AND METHOD - The present disclosure provides one embodiment of a semiconductor processing apparatus. The semiconductor processing apparatus includes a load lock designed to receive a wafer carrier; an inner wafer carrier buffer configured to hold the wafer carrier received from the load lock and to perform a nitrogen purge to the wafer carrier; and a processing module designed to perform a semiconductor process to wafers from the wafer. | 03-20-2014 |
20140244021 | SYSTEM AND METHOD OF MONITORING AN ENVIRONMENTAL PARAMETER ALONG A PREDETERMINED ROUTE - A monitoring system has a vehicle and a monitoring device. The vehicle is movable along a predetermined route, and the monitoring device is mounted to the vehicle. The monitoring device has a sensor configured to monitor an environmental parameter and a controller communicatively coupled to the sensor. The controller is configured to record the monitored environmental parameter along the predetermined route as data points associated with time tags, record position information, and associate the position information with corresponding time tags. The number of time tags associated with the position information is less than the number of time tags associated with the monitored environmental parameter. A server is configured to receive and display a visualized presentation of the recorded monitored environmental parameter and the recorded position information. | 08-28-2014 |
20150131070 | Photolithography System, Method for Transporting Photo-Mask and Unit Therein - A photolithography system includes a photo-mask storage, at least one photolithography machine and an overhead crane for transporting at least one photo-mask at least between the photo-mask storage and the photolithography machine. The overhead crane includes at least one main rail, a mask girder, a mask hoist and a mask holding device. The mask girder is coupled with the main rail and movable at least between a first position above the photo-mask storage and a second position above the photolithography machine. The mask hoist is movably coupled with the mask girder. The mask holding device is coupled with the mask hoist. | 05-14-2015 |
Hsiao-Hsuan Shen, Hsinchu TW
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20140347785 | SUPERCAPACITOR AND METHOD FOR MANUFACTURING ELECTRODE THEREOF - The present invention relates to a method for manufacturing an electrode of a supercapacitor, comprising: (A) providing a carbon substrate and a phosphorus-containing precursor, and mixing the carbon substrate and the phosphorus-containing precursor at a ratio of 1:100 to 1000:1 by weight; (B) heating the mixture of the carbon substrate and the phosphorus-containing precursor to a temperature between 300° C. and 1100° C. to obtain a P-doped carbon substrate; and (C) forming an electrode of a supercapacitor by using the P-doped carbon substrate. The present invention also relates to a supercapacitor which comprises: a first electrode; a second electrode; and an electrolyte that is interposed between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode is prepared by the above-mentioned method. | 11-27-2014 |
Hsin-Hsin Shen, Hsinchu TW
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20090280200 | HERBAL EXTRACTS WHICH INDUCE IMMUNE CELLS TO PRODUCE INTERFERON AND ACTIVATE TOLL-LIKE RECEPTORS - An herbal extract which induces immune cells to produce interferon and activates Toll-like receptors and a preparation method thereof are provided. The herbal extract is extracted from an effective amount of raw material including Glycyrrhizae Radix, Bupleuri Radix, Scutellariae Radix, Schisandrae Fructus and Paeoniae Rubra Radix. Glycyrrhizae Radix, Bupleuri Radix, Scutellariae Radix, Schisandrae Fructus and Paeoniae Rubra Radix have a weight ratio of 1-5:1-5:1-5:1-3:1-3. | 11-12-2009 |
20110251082 | BIOMARKERS FOR BREAST CANCER - The present invention uses 2-dimensional differential gel electrophoresisgel (2D-DIGE) and mass spetrum techniques to identify breast cancer biomarkers in transformed breast cells. In summary, the present invention identifies numerous putative breast cancer markers from various stages of breast cancer. The results of the invention aids in developing proteins identified as useful diagnostic and therapeutic candidates on breast cancer research. | 10-13-2011 |
Hui Tang Shen, Hsinchu TW
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20140183581 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device comprises a substrate; a first semiconductor layer formed on the substrate; a light-emitting layer on the first semiconductor layer; and a second semiconductor layer having a rough surface formed on the light-emitting layer, wherein the rough surface comprises a plurality of cavities randomly distributed on the rough surface, and one of the plurality of cavities has a substantially hexagonal shape viewed from top and a curved sidewall viewed from cross-section. | 07-03-2014 |
20140319559 | LIGHT-EMITTING DEVICE AND THE MANUFACTURING METHOD THEREOF - A light-emitting device includes: a light-emitting stack having an upper surface having a first surface roughness less than 0.2 nm; and an as-cut wafer comprising an irregularly uneven surface facing the light-emitting stack and having a second surface roughness greater than 0.5 μm. | 10-30-2014 |
Hui-Ting Shen, Hsinchu TW
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20150068799 | SUPPORT FOR DISPLAY - A support for a display which allows for the safe supply of electrical power when the display is reoriented includes a mounting board for mounting a display and a rack. The rack includes a power port and a power rail electrically connected to the power port. A slip assembly is slidable mounted on the rack. The mounting board is secured on the slip assembly. The slip assembly includes a conduction piece which is electrically connected to a display. The conduction piece is in electrical contact with different portions of the power rail when the slip assembly slides on the rack. | 03-12-2015 |
20150070584 | DISPLAY DEVICE USED AS DEMONSTRATION DEVICE - A demonstration device includes a handheld terminal and a receiving terminal. The handheld terminal includes a mode switch key, and a first micro control unit. The mode switch key can generate a mode switch trigger signal to change from TV signal mode for example, to whiteboard mode. The receiving terminal includes a second micro control unit, and a mode switch executing unit. The second micro control unit can receive the mode switch control signal, and the mode switch executing unit can switch the receiving terminal from TV signal mode to a whiteboard mode according to the mode switch control signal. The receiving terminal draws a picture with lines of particular colors and widths according to movements of the handheld terminal when held in a user's hand. | 03-12-2015 |
Hung-Che Shen, Hsinchu TW
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20090267229 | CHIP PACKAGE STRUCTURE - A chip package structure is provided. The chip package structure comprises different layers of leads electrically connected to different circuits of a chip. The chip package structure comprises a chip and a flexible substrate layer. The chip has an active surface, a plurality of first pads, and a plurality of second pads. The first pads and the second pads are disposed on the active surface. The flexible substrate layer has a first conductive layer, a second conductive layer, a first surface, and a second surface opposite the first surface. The flexible substrate layer has an opening defined therein. The first conductive layer is formed on the first surface of the flexible substrate layer. The first conductive layer includes a plurality of first leads. The first leads electrically connect to the first pads. The second conductive layer is formed on the second surface of the flexible substrate layer. The second conductive layer includes a plurality of second leads. The second leads extend inwards into the opening and electrically connect to the second pads through the opening. | 10-29-2009 |
20130032940 | CHIP PACKAGE STRUCTURE - A chip package structure includes a chip, a flexible substrate, first leads and second leads. First bumps, second bumps and a seal ring are disposed on an active surface of the chip. The first and second bumps are respectively adjacent to first and second edges of the chip. The seal ring is located between the bumps and the edges. The chip is disposed in a chip mounting region of the flexible substrate. The first and second edges correspond to first and second sides of the chip mounting region respectively. The first leads disposed on the flexible substrate enter the chip mounting region through the first side and extend toward the second side to electrically connect the second bumps respectively. The second leads disposed on the flexible substrate enter the chip mounting region through the second side and extend toward the first side to electrically connect the first bumps respectively. | 02-07-2013 |
Jian-Yuan Shen, Hsinchu TW
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20080291733 | LOADING DATA WITH ERROR DETECTION IN A POWER ON SEQUENCE OF FLASH MEMORY DEVICE - A semiconductor device is provided to have two groups of nonvolatile memory cells, two groups of data registers and a compare circuit. Each of the two groups of the nonvolatile memory cells stores a set of predetermined data and a set of complementary data respectively. The two groups of data registers are respectively connected to the two groups of the nonvolatile memory cells. The compare circuit is connected to the two groups of the data registers, for performing a comparison to generate a compare result. | 11-27-2008 |
Jui-Chang Shen, Hsinchu TW
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20130342818 | PROJECTION DEVICE AND LENS MODULE - A projection device includes a main body, a light source, a light valve, and a lens module. The light source produces an illumination beam. The light valve converts the illumination beam into an image beam. The lens module disposed at the main body includes a lens barrel and a lens. The lens barrel has an inner wall, a containing space and a riveting portion. The inner wall surrounds the containing space. The riveting portion is located in the containing space. There is a gap between the riveting portion and the inner wall. The lens disposed in the containing space has a light emitting surface and a side surface. The side surface leans against the riveting portion. An end of the riveting portion extends to the light emitting surface to limit the lens in the containing space The image beam passes through the lens to form a projection beam. | 12-26-2013 |
Kuo-Wei Shen, Hsinchu TW
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20160005915 | METHOD AND APPARATUS FOR INHIBITING LIGHT-INDUCED DEGRADATION OF PHOTOVOLTAIC DEVICE - A method for inhibiting light-induced degradation of a photovoltaic device includes steps of: a) subjecting the photovoltaic device to an illumination treatment using a light having a wavelength not less than 300 nm to heat the photovoltaic device in the absence of ambient light; and b) maintaining the temperature of the photovoltaic device above an annealing temperature of the photovoltaic device for at least 0.5 minute. An apparatus for inhibiting light-induced degradation of a photovoltaic device is also disclosed. | 01-07-2016 |
Leo Shen, Hsinchu TW
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20080257590 | HIGH THERMAL CONDUCTING CIRCUIT SUBSTRATE AND MANUFACTURING PROCESS THEREOF - A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself. | 10-23-2008 |
Min-Hung Shen, Hsinchu TW
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20150123477 | POWER INTEGRATED DEVICE AND POWER CONTROL METHOD THEREOF - The present invention provides a power integrated device including a detection circuit and a determination circuit. The detection circuit detects whether first and second connection ports are coupled to a power source and produce first and second valid signals, respectively, and detect whether the power source coupled to the first and second connection ports meet first or second predetermined power values and produce first and second power spec signals, respectively. The determination circuit produces a system power-control signal according to the first valid signal, the second valid signal, the first power spec signal and the second power spec signal to turn on or turn off the power integrated device. | 05-07-2015 |
Pei-Yi Shen, Hsinchu TW
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20090174858 | Array Substrate Adapted for Liquid Crystal Display Device and Liquid Crystal Display Device - An array substrate adapted for a liquid crystal display (LCD) device and the liquid crystal display device are provided. The LCD device includes an opposing substrate, an array substrate, and a liquid crystal layer. The array substrate is disposed opposite to the opposing substrate, and the liquid crystal layer is filled therebetween. The array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of switching devices, and an insulating layer. The scan lines are substantially perpendicular to the data lines to define a plurality of array pixels. The switching devices are connected to the corresponding scan lines and the data lines. The insulating layer is deposited above the scan lines and the data lines, and has a plurality of free ends. Two of the free ends define a broken region. Each of the free ends has a tilt down profile with a decreasing width facing the broken region. The profile can avoid the short circuiting between the two adjacent array pixels, which is caused by the residual transmissive electrode during the process. | 07-09-2009 |
Ping-Fei Shen, Hsinchu TW
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20100166033 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device includes a substrate, a first cladding layer over the substrate, an active region on the first cladding layer, and a second cladding layer on the active region, wherein the active region includes a first type barrier layer that is doped and a second type barrier layer that is undoped, the first type barrier layer being closer to the first cladding layer than the second type barrier layer. | 07-01-2010 |
Sheng-Chih Shen, Hsinchu TW
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20080284860 | Image stabilization driving device - An image-stabilizing driving device is proposed, including a slidable block coupled to an image sensor, a flat surface acoustic wave actuator for contacting with and driving the slidable block to move on a surface contacted therewith, and a contactless force action unit having a first and a second contactless force action layers. The first contactless force action layer is formed between the slidable block and the image sensor and the second contactless force action layer is formed on a bottom surface of the flat surface acoustic wave actuator, thereby providing preload force for the slidable block to contact with flat surface ascoustic wave actuator so as to form a thin image-stabilizing driving device. | 11-20-2008 |
Sheng-Kun Shen, Hsinchu TW
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20130250852 | NETWORK COMMUNICATION STRUCTURE, NETWORK COMMUNICATION SYSTEM AND NETWORK COMMUNICATION METHOD - A network communication structure, system and method are disclosed in the invention. The network communication structure includes client devices, a power line network and access points. One of the access points is connected to an external internet. The access points are all connected in the power line network, such that a first local area network is formed between the access points. Each of the access points utilizes an omni-directional antenna to form a local area sub-network between the access point and a client device. Each of the access points utilizes a directional antenna to form a second local area network between access points. According to a network quality of the power line network, each of the access points transmits an information packet to another access point via the first local area network or the second local area network. | 09-26-2013 |
20140036678 | Load Balancing Method and Related Wireless Communication Device - A load balancing method for a wireless communication device includes checking a total loading of the wireless communication device, wherein the total loading comprises a first loading of an omni antenna and a second loading of a directional antenna; and adjusting transmission power of the wireless communication device according to the total loading of the wireless communication device and information sent by at least one neighbor wireless communication device, in order to perform load balancing. | 02-06-2014 |
20140133585 | POWER LINE COMMUNICATION SYSTEM AND CONTROL METHOD THEREOF - A power line communication system includes a power distribution device connected to two power lines, a plurality of power line communication devices and a first coupler device electrically connected between the first power line and the second power line. The first coupler device is configured at the last end of the power line communication system. Before a transmitting device transmits data to a receiving device, the first coupler device determines whether to couple the power lines with each other according a first signal quality between the transmitting and the receiving device when the power lines are not coupled with each other and a second signal quality between the transmitting and the receiving device when the power lines are coupled with each other. | 05-15-2014 |
Shih-Chung Shen, Hsinchu TW
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20090115126 | Feed Detecting System - A feed detecting system includes a sending element, a receiving element, a filtering-amplifying circuit, a peak-holding circuit, an A/D converter and a processing unit. The receiving element receives an ultrasonic signal sent by the sending element, and then outputs an electric signal, the filtering-amplifying circuit receives, filters and amplifies the electric signal, the A/D converter converts the electric signal to a digital signal, the processing unit reads the digital signal and compares the digital signal with a standard value stored in the processing unit. In this present invention, the A/D converter can be a low frequency A/D converter, so the cost of the feed detecting system is reduced. | 05-07-2009 |
Shih-Guo Shen, Hsinchu TW
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20090098714 | Method for forming III-nitrides semiconductor epilayer on the semiconductor substrate - GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate. | 04-16-2009 |
Shih-Jye Shen, Hsinchu TW
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20100014359 | OPERATING METHOD OF NON-VOLATILE MEMORY - An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a second conductive type source region. In operating such a non-volatile memory, voltages are applied to the gate, the second conductive type drain region, the second conductive type source region and the first conductive type silicon body layer beneath the gate, to inject electrons or holes in to the charge storage structure or evacuate the electrons from the charge storage structure by a method selected from a group consisting of channel hot carrier injection, source side injection, band-to-band tunnelling hot carrier injection and Fowler-Nordheim (F-N) tunnelling. | 01-21-2010 |
20110057243 | NON-VOLATILE MEMORY WITH A STABLE THRESHOLD VOLTAGE ON SOI SUBSTRATE - A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate. | 03-10-2011 |
Shin-Jang Shen, Hsinchu TW
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20120293260 | Low-Offset Current-Sense Amplifier and Operating Method Thereof - A low-offset current-sense amplifier and an operating method thereof are disclosed. The low-offset current-sense amplifier includes a sense amplifier, a first current supply unit, a second current supply unit, and a processing unit. The first current supply unit is coupled to the sense amplifier, and includes a first transistor group and a first current output terminal. The second current supply unit is coupled to the sense amplifier, and includes a second transistor group and a second current output terminal. The processing unit controls the on/off of some transistors of the first transistor group and the second transistor group according to electric currents output from the first current output terminal and the second current output terminal, respectively. | 11-22-2012 |
20120294090 | Current-Sense Amplifier With Low-Offset Adjustment and Method of Low-Offset Adjustment Thereof - A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier. | 11-22-2012 |
20150123192 | MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. | 05-07-2015 |
20150333736 | METHOD AND CIRCUIT FOR TEMPERATURE DEPENDENCE REDUCTION OF A RC CLOCK CIRCUIT - A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage. | 11-19-2015 |
20160064086 | CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY - A circuit for adjusting a select gate voltage of a non-volatile memory is provided. The circuit includes a well, a select gate, an adjustment unit, and a switch. There is a capacitive coupling between the well and the select gate. The adjustment unit generates a driving voltage for the select gate. The switch is coupled in series with the adjustment unit between the select gate and the well. | 03-03-2016 |
Tzu-Shih Shen, Hsinchu TW
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20080308925 | FABRICATING PROCESS AND STRUCTURE OF THERMAL ENHANCED SUBSTRATE - A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. First, a metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. | 12-18-2008 |
20090288859 | NON-CYLINDER VIA STRUCTURE AND THERMAL ENHANCED SUBSTRATE HAVING THE SAME - A thermal enhanced substrate having a non-cylinder via structure includes at least a metal layer disposed on an insulating base material and a number of thermal channels respectively constituted by at least a trough pattern penetrating the insulating base material and a conductive material deposited in the trough pattern. The trough pattern serves as a non-cylinder via structure having at least an elongated hole for heat dissipations so as to reduce a working temperature of an electronic device. | 11-26-2009 |
20100206463 | FABRICATING PROCESS OF THERMAL ENHANCED SUBSTRATE - A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. A metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks. | 08-19-2010 |
20130043016 | STRUCTURE AND PROCESS OF HEAT DISSIPATION SUBSTRATE - Structure of a heat dissipation substrate including a metal substrate, a first insulating material, a second insulating material, a first patterned conductive layer and a second patterned conductive layer is provided. The metal substrate has an upper surface and a lower surface opposite to each other, a plurality of first recesses located on the upper surface and a plurality of second recesses located on the lower surface. The first insulating material is provided to fill into the first recesses. The second insulating material is provided to fill into the second recesses. The first patterned conductive layer is disposed on the upper surface of the metal substrate and a portion of the first insulating material. The second patterned conductive layer is disposed on the lower surface of the metal substrate and a portion of the second insulating material. | 02-21-2013 |
20130260018 | PROCESS OF FABRICATING HEAT DISSIPATION SUBSTRATE - A process of fabricating a heat dissipation substrate is provided. A metal substrate having an upper surface, a lower surface, first recesses located on the upper surface and second recesses located on the lower surface is provided. The metal substrate is divided into carrier units and connecting units connecting the carrier units. A first and a second insulating materials are respectively filled into the first and the recesses. A first conductive layer is formed on the upper surface and the first insulating material. A second conductive layer is formed on the lower surface and the second insulating material. The first and the second conductive layers are patterned to form a first and a second patterned conductive layers. The first and the second insulating materials are taken as an etching mask to etch the connecting units of the metal substrate so as to form a plurality of individual heat dissipation substrates. | 10-03-2013 |
Wan-Wan Shen, Hsinchu TW
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20090144405 | Apparatus And Method For Presence Service On Inter-Domain - Disclosed is an apparatus and method for presence service on inter-domain. The apparatus comprises an enhanced inter-domain presence (EIP) module and an enhanced inter-domain presence authorization document (EIPAD) module. When at least a watcher requests a presence subscription to a foreign domain, the EIP module dynamically aggregates the foreign domain presentities for all local watchers having the subscription request, and produces a foreign domain document (FDD). The EIP module also acts as a presence client having the subscription for foreign-domain, and dispatches presence status information. The enhanced inter-domain presence authorization document module resolves the FDD contents, identifies the subscribed foreign-domain presentities, then accesses a corresponding presence authorization document and notifies it to the presence server on the watcher domain. | 06-04-2009 |
Wei-Ming Shen, Hsinchu TW
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20110254460 | LIGHT EMITTING CONTROL DEVICE AND METHOD THEREOF FOR LIGHT EMITTING DIODE PRINT HEAD - A light emitting control device for a light emitting diode print head includes a control unit, a pulse-mask unit, a strobe unit and a data output unit. The pulse-mask unit outputs n clock signals in sequence to a light emitting diode print head. The strobe unit outputs a strobe signal to the light emitting diode print head, so as to switch on the light emitting diode print head. The data output unit outputs a print data signal to the light emitting diode print head. When the pulse-mask unit outputs a k-th clock signal of the n clock signals, the pulse-mask unit delays the k-th clock signal for a predetermined time, and the data output unit pauses outputting the print data signal. After the predetermined time, the pulse-mask unit and the data output unit continue to output the rest of the clock signals and the print data signal. | 10-20-2011 |
Wen-Peng Shen, Hsinchu TW
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20140071671 | T-BAR LAMP - A T-bar lamp includes a T-bar lamp housing, at least one light source, and a pattern. The T-bar lamp housing has an opening. The light source is mounted in the T-bar lamp housing. The pattern covers the opening and has at least one transparent region. The transparent region exposes the corresponding light source. | 03-13-2014 |
Yi-Lun Shen, Hsinchu TW
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20090016413 | PSEUDO RANDOM CLOCK GENERATOR - A pseudo random clock generator includes a clock generator for generating a clock signal. A pseudo random code generator receives the clock signal and thereby generating a pseudo random code. A code limiter enables the value of the pseudo random code being unchanged for at least two periods of the clock signal. A logic gate applies a logic operation to the pseudo random code and the clock signal and thereby outputting a pseudo random clock. | 01-15-2009 |
Ying-Yuan Shen, Hsinchu TW
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20090059186 | LAMP HOLDER OF A PROJECTION APPARATUS AND FABRICATION THEREOF - A method for forming a lamp holder. The lamp holder is applied in a projection apparatus. First, the lamp holder comprising metal is provided. An insulating layer is formed on one surface of the lamp holder to insulate the lamp holder from another element of the projection apparatus. | 03-05-2009 |
Yuhren Shen, Hsinchu TW
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20110164206 | LIQUID CRYSTAL DISPLAY DEVICE - The present invention provides an improved type of liquid crystal (LC) display device with wide-viewing angle and high optical transmittance. The LC display of the present invention consists of: at least one LC alignment apparatus, which makes the LC molecules within the display area forming a continuous-domain or multi-domain alignments, and hence improve its wide-viewing-angle characteristics; a LC layer formed by Nematic type LC with chiral dopants, and with optimal parameters of the optical path difference Δnd and LC rotations of d/p ratio, such that LC molecules can be aligned along all radial directions to achieve optimal transmittance, and thus producing an wide-viewing-angle LC display improved transmittance without the formation of dark fringes in the display area. | 07-07-2011 |
20110199550 | LIQUID CRYSTAL DISPLAY DEVICE - A new type of liquid crystal display (LCD) device with improved high transmittance and wide-view-angle characteristics while without gray-level inversion at an inclined viewing angle is provided. The LCD device includes a first substrate with common electrodes, a second substrate with at least one pixel unit, a liquid crystal (LC) layer disposed between the first substrate and the second substrate, a first polarizer, and a second polarizer. The pixel unit has a pixel electrode, which is formed by at least one dense electrode area and at least one sparse electrode area. The LC molecules of the LC layer form a continuous-domain alignment after being driven by a voltage. | 08-18-2011 |
Yuh-Ren Shen, Hsinchu TW
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20080198516 | Electrostatic discharge (ESD) protection device and method therefor - A method and device for providing electrostatic discharge (ESD) protection are disclosed. The method uses the gate-controlled conductivity of field n-channel metal-oxide-semiconductor field effect transistor (field NMOSFET), wherein considerable ESD current can be conducted away when any ESD event beyond range of operation voltage, unlike PMOS ESD protection which is to be turned on at negative voltage. Instead of the traditional two-stage ESD protection (using one ESD protection between open drain output and V | 08-21-2008 |
20080266236 | Driving method of liquid crystal display device having dynamic backlight control unit - A dynamic control method for controlling backlight module of liquid crystal display (LCD) comprises steps of: receiving a frame data which is transferred to the LCD and consists a plurality of raw grayscale level; processing a statistical analysis for distribution of the plurality of raw grayscale level; and transferring a plurality of corrected grayscale level which is resulted from the statistical analysis corresponding to the raw grayscale level to the backlight control unit and a data modification simultaneously, wherein the backlight control unit uses the plurality of corrected grayscale level to modify brightness of backlight module and the data modification uses the plurality of corrected grayscale level to compare with the plurality of raw grayscale level for accurate display performance, so that the electrical power consumption is reduced and image quality is enhanced. | 10-30-2008 |
20090267971 | METHOD FOR DRIVING DISPLAY DEVICE TO HIDE TRANSIENT BEHAVIOR - The major characteristics of the present invention lies in that, on one hand, conventional driving or overdriving techniques that do not add significant cost to the display device are used for scanning while, on the other hand, the direct-lit, LED-based backlight is turned off during the pixels' transient period where their grey levels gradually approach or overshoot above the target grey levels so that the residuals of the dynamic images during the transient period are not manifested. | 10-29-2009 |
20090267972 | METHOD FOR DRIVING DISPLAY DEVICE TO HIDE TRANSIENT BEHAVIOR - The major characteristics of the present invention lies in that, on one hand, conventional driving or overdriving techniques that do not add significant cost to the display device are used for scanning while, on the other hand, the direct-lit, LED-based backlight is turned off during the pixels' transient period where their grey levels gradually approach or overshoot above the target grey levels so that the residuals of the dynamic images during the transient period are not manifested. | 10-29-2009 |
Yu-Jiun Shen, Hsinchu TW
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20100276724 | LIGHT-EMITTING DEVICE - The application illustrates a light-emitting device including a contact layer and a current spreading layer on the contact layer. A part of the contact layer is a rough structure and a part of the contact layer is a flat structure. A part of the current spreading layer is a rough structure and a part of the current spreading layer is a flat structure. The rough region of the contact layer and the rough region of the current spreading layer are substantially overlapped. | 11-04-2010 |
20120142142 | METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure is disclosed, which includes providing a substrate comprising a bottom surface and a growth surface opposite to the bottom surface; forming a buffer layer comprising a first surface which is not a C-plane substantially parallel with the bottom surface on the growth surface; forming a semiconductor structure on the buffer layer; forming at least one cavity in the buffer layer; extending the cavity along a main extending direction; separating the substrate and the semiconductor structure; wherein the main extending direction is substantially not parallel with the normal direction of the first surface. | 06-07-2012 |
20140103290 | LIGHT-EMITTING DEVICE - A light-emitting device comprises a first semiconductor layer; a second semiconductor layer; a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer; a first electron blocking layer formed between the first semiconductor layer and the light-emitting layer; and a second electron blocking layer formed between the second semiconductor layer and the light-emitting layer, wherein the thickness of the second electron blocking layer is not equal to that of the first electron blocking layer, and/or the band gap energy of the second electron blocking layer is not equal to that of the first electron blocking layer. | 04-17-2014 |
Yun-Chung Shen, Hsinchu TW
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20160103096 | BIOCHEMICAL TEST CHIP AND METHOD FOR MANUFACTURING THE SAME - Provided is a biochemical test chip including an insulating substrate, an electrode unit, a first insulating septum, a reactive layer and a second insulating septum. The insulating substrate has a first vent hole. The electrode unit is located on the insulating substrate. The first insulating septum is located on the electrode unit. The first insulating septum has an opening which exposes a part of the electrode unit. The reactive layer is located in the opening. The second insulating septum is located on the first insulating septum. The second insulating septum has a second vent hole. The first vent hole is at least partially overlapped with the second vent hole. | 04-14-2016 |
Yun-Yong Shen, Hsinchu TW
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20090299669 | Method of yield management for semiconductor manufacture and apparatus thereof - A method of yield management for semiconductor manufacture and an apparatus thereof are provided. The method includes the following steps. Defect data of a layer of a semiconductor wafer is obtained, wherein the defect data includes sizes and locations of defects with respect to the layer. A layout with respect to the layer is obtained. And a critical area analysis is performed in parallel for the layer by a plurality of processing devices according to the defect data and the layout to determine locations of defects falling into a critical area of the layer among the locations of the defects. | 12-03-2009 |