Patent application number | Description | Published |
20110078388 | FACILITATING MEMORY ACCESSES - In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted. | 03-31-2011 |
20110112820 | Reusing Invalidated Traces in a System Emulator - Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed. | 05-12-2011 |
20110113223 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 05-12-2011 |
20120331262 | PERFORMING MEMORY ACCESSES WHILE OMITTING UNNECESSARY ADDRESS TRANSLATIONS - In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted. | 12-27-2012 |
20140059331 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 02-27-2014 |
20140059332 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction. | 02-27-2014 |
Patent application number | Description | Published |
20100192137 | METHOD AND SYSTEM TO IMPROVE CODE IN VIRTUAL MACHINES - A computer readable storage medium is provided having executable instructions stored thereon for executing a method of operating a computing system, in which an inner virtual machine translates first instructions, which are supported by the inner virtual machine, into second instructions, which are supported by an outer virtual machine. The method includes encoding, in the inner virtual machine, third instructions into the second instructions into which the first instructions are translated, the third instructions including hints for facilitating an execution of the second instructions, and, in an event the hints are supported by the outer virtual machine, initiating the execution of the second instructions while utilizing the hints by the outer virtual machine to achieve an increased efficiency of the execution of the second instructions. | 07-29-2010 |
20110071813 | Page Mapped Spatially Aware Emulation of a Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 03-24-2011 |
20110071814 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 03-24-2011 |
20110071815 | Host Cell Spatially Aware Emulation of a Guest Wild Branch - A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed. | 03-24-2011 |
20110071816 | Just In Time Compiler in Spatially Aware Emulation of a Guest Computer Instruction Set - A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell. | 03-24-2011 |
20130198498 | COMPILING METHOD, PROGRAM, AND INFORMATION PROCESSING APPARATUS - A method, program, and apparatus for optimizing compiled code using a dynamic compiler. The method includes the steps of: generating intermediate code from a trace, which is an instruction sequence described in machine language; computing an offset between an address value, which is a base point of an indirect branch instruction, and a start address of a memory page, which includes a virtual address referred to by the information processing apparatus immediately after processing a first instruction; determining whether an indirect branch instruction that is subsequent to the first instruction causes processing to jump to another memory page, by using a value obtained from adding the offset to a displacement made by the indirect branch instruction; and optimizing the intermediate code by using the result of the determining step. | 08-01-2013 |
20130231913 | Self Initialized Host Cell Spatially Aware Emulation of a Computer Instruction Set - A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction. When an instruction is to be emulated for the first time, the initialization routine patches itself with the discovered semantic routine such that subsequent emulation of the Guest instruction can be directly performed | 09-05-2013 |
20140136179 | Page Mapped Spatially Aware Emulation of Computer Instruction Set - Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page. | 05-15-2014 |
Patent application number | Description | Published |
20110306771 | AVOIDANCE OF NON-SPECIFIC BINDING ON AN ACOUSTIC WAVE BIOSENSOR USING LINKER AND DILUENT MOLECULES FOR DEVICE SURFACE MODIFICATION - An acoustic wave biosensor comprising a surface of a mixed self-assembling monolayer for receiving a probe-biomolecule is described herein. The biosensor surface may comprise a piezoelectric quartz crystal,—for detection purposes with the electromagnetic piezoelectric acoustic sensor (EMPAS)—upon which a mixed self-assembling monolayer is formed, which includes at least one linker, such as 2,2,2-trifluoroethyl-13-trichlorosilyl-tridecanoate (TTTA); its oligoethylene glycol (OEG) analog OEGylated TTTA (OEG-TTTA); S-(2-(2-(2-(3-trichlorosilyl-propyloxy)-ethoxy)-ethoxy)-ethyl)-benzenethiosulfonate (OEG-TU BTS). Linker/diluent systems for attaching a functionalizing entity to the surface of a biosensor are described, as well as methods for preparing a biosensor surface with an oligoethylene glycol linker. | 12-15-2011 |
20140018463 | MODIFICATION OF BIOMEDICAL POLYMERS FOR PREVENTION OF FOULING AND CLOTTING - A surface-modified polymer is described, comprising a polymeric material and a self-assembling monolayer covalently bound thereto. The monolayer comprises monoethylene glycolated-OH (MEG-OH); 2-(3-trichlorosilyl-propyloxy)-ethyl-trifluoroacetate (7-OEG or MEG-TFA); 2,2,2-trifluoroethyl-13-trichlorosilyl-tridecanoate (TTTA); OEGylated TTTA (OEG-TTTA); S-(2-(2-(2-(3-trichlorosilyl-propyloxy)-ethoxy)-ethoxy)-ethyl)-benzenethiosulfonate (OEG-TUBTS); or a combination thereof. Methods are described for forming a surface-modified polymer by surface activation, such as with plasma. By utilizing the surface-modified polymer to make medical equipment or devices for contacting biological fluids, a reduction in surface fouling and thrombus formation can result. Advantageously, polymeric equipment or components so modified may have a reduction in unwanted chemical interactions leading to fouling or clotting. Short trichlorosilane surface modifiers allow films to be deposited onto poly(ethylene terephthalate), polycarbonate, polypropylene, polyvinyl chloride, polyurethane, and other polymers activated using plasma. | 01-16-2014 |