Patent application number | Description | Published |
20140130163 | Method and Apparatus for Setting Secure Connection in Wireless Communications System - A method of setting a secure connection in a wireless communications system is disclosed. The method comprises setting a protocol information to a terminal; and checking a packet received in the terminal according to the protocol information; wherein the packet comprises a protocol type, a source port, and a destination port. | 05-08-2014 |
20140341111 | LINKING METHOD BETWEEN COMMUNICATION DEVICES AND RELATED MACHINE READABLE MEDIUM - A linking method employed by a first communication device includes: transmitting a first network domain information to a second communication device before/after a link with the second communication device is established; receiving a second network domain information from the second communication device before/after the link with the second communication device is established; and when the first communication device is decided to be a group owner before/after the link with the second communication device is established, determining a network domain address of the link according to the first network domain information and the second network domain information. | 11-20-2014 |
20140355583 | WIRELESS COMMUNICATING METHOD AND ELECTRONIC SYSTEM UTILIZING THE WIRELESS COMMUNICATING METHOD - A wireless communicating method for building direct communication between a first electronic device and a second electronic device. The wireless communicating method comprises: (a) controlling the first electronic device and the second electronic device to exchange communicating information of each other, wherein the communicating information comprises first password information, and comprises at least one of first IP information and first service information; and (b) after the step (a), confirming the first password information. | 12-04-2014 |
20150181239 | Method and Apparatus for frame rate control in Transmitter of Wireless Communications System - A method for frame rate control in a transmitter of a wireless communications system is disclosed. The method comprises generating a frame and a first information corresponding to a first expiration time of the frame by a frame generating module; handling the frame according to the first expiration time by the driver module; and informing the frame generating module an adjusting information according to a first pre-determined rule by the driver module. | 06-25-2015 |
20150181469 | METHODS FOR MANAGING RADIO RESOURCES BETWEEN MULTIPLE RADIO MODULES AND COMMUNICATIONS APPARATUS UTILIZING THE SAME - Communications apparatus includes first and second radio modules and an antenna array coupled to the first and the second radio modules and includes multiple antennas. When the first and the second radio modules operate at the same time, the first radio module negotiates with a first communications device an amount of antenna(s) to be used by a first message, so that the first radio module operates with the amount of the antenna(s) and second radio module operates with at least one of the remaining antenna(s). | 06-25-2015 |
Patent application number | Description | Published |
20140035474 | HIGH EFFICIENCY LED DRIVER CHIP AND DRIVER CIRCUIT THEREOF - Disclosed is a high-efficiency LED driver chip and a driver circuit of the chip, and the driver chip includes a detection unit, a comparison unit and a correction unit. The LED detection unit detects the operating current of the LED driver circuit by an external sensing resistor and an internal current mirror to output a setup signal, and the comparison unit detects the driving current of at least one LED by an external comparing resistor to output an initialization signal, so that the correction unit can output a correction signal according to the setup signal and the initialization signal to reduce the power loss of the circuit while maintaining the driving current constant, so as to improve the illumination quality and the service life of the LED. | 02-06-2014 |
20140292229 | ELECTROMAGNETIC COUPLING MULTI-OUTPUT CONTROL CIRCUIT - Disclosed is an electromagnetic coupling multi-output control circuit having a detection unit, a switching unit and a coupling unit, and the coupling unit is coupled to a side of a transformer of a power driving device to sense and produce a second driving voltage, such that the transformer has a multi-output function. The switching unit is provided for receiving and outputting the second driving voltage to a second driving load, and the detection unit is provided for detecting the second driving voltage to produce a detection value, so that the switching unit analyzes the detection value and switches outputting a frequency of the second driving voltage to stabilize the voltage value of the second driving voltage, so as to flexibly increase the number of output voltages of the power driving device while lowering the cost and expand the scope of applicability. | 10-02-2014 |
20140333215 | MULTI-SEGMENT LED DRIVING CIRCUIT - Disclosed is a multi-segment LED driving circuit used in an AC operating mode for outputting a drive current to drive a plurality of serially connected LED strings. The LED driving circuit includes at least one detection part, at least one comparison part and at least one adjusting part. The detection part detects an input voltage and an output voltage at both ends of each string and its next string to form a detected value provided for the comparison part to compare the detected value with a reference value to turn on or off the adjusting part so as to control the strings through which the drive current passes and then sequentially drives the strings to emit light. The LED driving circuit can adjust the load of the circuit immediately based on the change of voltage value of the AC power to ensure the stability of the drive current. | 11-13-2014 |
Patent application number | Description | Published |
20150204907 | ELECTRICAL TESTING DEVICE - An electrical testing device includes a base having two parallel first rails, a platform provided on the base, a support provided between the first rails, a test arm, a rotary table provided on the test arm, a plurality of holders provided on the rotary table, and a plurality of probe sets respectively provided on the holders. The support has a second rail provided thereon, and is moveable relative to the base and the platform. The test arm is provided on the second rail and above the platform, wherein the test arm is moveable along with the support, and is also movable relative to the support. The rotary table is moveable or rotatable relative to the test arm. The holders are moveable along with the rotary table, and are also moveable or rotatable relative to the rotary table. The probe sets are moveable along with the holders. | 07-23-2015 |
20150204908 | ELECTRICAL TESTING MACHINE - An electrical testing machine includes a base having two parallel first rails, a platform provided on the base, a probe holder provided on the base and having a plurality of placement locations, a support provided between the first rails and having a second rail thereon, a test arm provided on the second rail and above the platform, a receiving seat provided on the test arm, and a plurality of probe sets, wherein one of the probe sets is engaged on the receiving seat, while the others are respectively provided on the placement locations. The support is movable relative to the base and the platform. The test arm is movable along with the support, and is also movable relative to the support. The receiving seat is movable or rotatable relative to the test arm. The probe set engaged on the receiving seat is movable along with the receiving seat. | 07-23-2015 |
20150204962 | METHOD OF OPERATING TESTING SYSTEM - A method of operating a testing system is provided, wherein the testing system has a test machine and a probe module, which has a first probe set and a second probe set. One of the first probe set and the second probe set can be connected to the test machine. The method includes the following steps: connect the test machine and the first probe set; calibrate the testing system; abut the first probe set against a DUT to do electrical tests; disconnect the first probe set and the DUT; disconnect the test machine and the first probe set; connect the test machine and the second probe set; calibrate the testing system again; abut the second probe set against the DUT to do electrical tests. | 07-23-2015 |
20150212186 | METHOD OF CALIBRATING AND OPERATING TESTING SYSTEM - A method of calibrating and operating a testing system is provided, wherein the testing system has a test machine, a conducting wire set, a calibration module, and a probe module. The method includes the following steps: electrically connect the test machine and the conducting wire set; electrically connect the conducting wire set and the calibration module; send out electrical signals from the test machine to the calibration module for doing at least one test among a short-circuit test, an open-circuit test, and an impedance test, and then calibrate the testing system by correspondingly performing compensation based on results of these tests; electrically disconnect the conducting wire set and the calibration module, and electrically connect the conducting wire set and the probe module; abut the probe module against a DUT; send out electrical signals from the test machine to the probe module to do electrical tests on the DUT. | 07-30-2015 |
20150233969 | Testing system and method for testing of electrical connections - A testing system includes a test machine, a plurality of probe sets, a data input device, a controller, a memory, and a data output device. The test machine has a platform for a DUT to be placed thereon, and a test arm which is movable relative to the platform. The probe sets are provided on the test machine with at least one probe set provided on the test arm to contact the DUT. The data input device is used to input information about the DUT. The controller is electrically connected to the test arm, the probe set on the test arm, and the data input device to move the test arm to a predetermined position according to the inputted information, and to make the probe set contact the DUT for electrical test. The memory saves electrical test result, which is outputted by the data output device. | 08-20-2015 |
20150241544 | METHOD OF CALIBRATING AND DEBUGGING TESTING SYSTEM - A method of calibrating and debugging a testing system is provided. First, values of different electrical path segments are calibrated, and parameters of the electrical path segments while being calibrated are saved. After calibration, electrical tests can be processed on a DUT. If the testing system malfunctions, the values of the electrical path segments are calibrated again to compare the current parameters to the previously saved parameters. The component which goes wrong can be found out quickly in this way. | 08-27-2015 |
Patent application number | Description | Published |
20110062052 | Front Opening Unified Pod disposed with purgeable supporting module - A Front Opening Unified Pod (FOUP) having a purgeable supporting module disposed at the junction of each sidewall and the backwall of the container, the characteristic of the FOUP being in that: the purgeable supporting module has a buffer gas chamber and a gas inlet is disposed at one end of the buffer gas chamber and connected to a gas valve on the bottom surface, an outgassing channel is disposed on the purgeable supporting module facing the opening of the FOUP, and a long slot is disposed on one side of the outgassing channel, an airflow channel being disposed between and thus connecting the outgassing channel and the buffer gas chamber, and a plurality of supporting ribs being vertically disposed on one side of the long slot at intervals. | 03-17-2011 |
20110253591 | Reticle Pod Having Function of Gas Exchange - A reticle pod for storing reticles, into the gas channel of partition of which gas is filled through a gas inlet, wherein strong gas flow is formed around the pellicle film and the pellicle film expands outward in accordance with the Bernoulli's principle; when no gas is filled in through the gas inlet, the pellicle film contracts inward. Therefore, by turning on and shutting off the gas inlet valve, the pellicle film will be set in a breathing motion for the gas inside the pellicle film to be exchanged. | 10-20-2011 |
20110297579 | Wafer container with elasticity module - A wafer container, comprising: a container body, the container body having a plurality of slot portions on two opposite sidewalls of the interior of the container body for horizontally sustaining a plurality of wafers, each slot portion having a horizontal carrying portion, an opening being formed on one side of the container body for exporting and importing a plurality of wafers; and a door, said door having an inner surface and a outer surface, the inner surface being joined with the opening of the container body for protecting the plurality of wafers therein, the characteristic in that: an elasticity module is disposed on the inner wall of the rear end of the container body opposite to the opening, the elasticity module having a rectangular body and a convex portion bending toward the interior of the container body being respectively formed on two longer opposite sides of the rectangular body. | 12-08-2011 |
20120018347 | Reticle POD with Sensor - An EUV pod with pressure sensors disposed between its inner container and outer container, wherein pressure sensors disposed on the inner side of the outer container are used to detect the pressure between the outer container and the inner container, and the pressure data are used to determine whether the inner container is firmly fastened by the outer container. | 01-26-2012 |
Patent application number | Description | Published |
20120228723 | GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure. | 09-13-2012 |
20120264267 | METHOD FOR FABRICATING MOS TRANSISTOR - A method of fabricating a MOS transistor includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a first spacer on the sidewall of the gate structure and forming at least a recess within the substrate next to the first spacer; performing an oxygen-containing process to form an oxygen-containing layer on the surface of the recess; performing a cleaning process to remove the oxygen-containing layer; performing an epitaxial process to form an epitaxial layer in the recess; and removing the first spacer. | 10-18-2012 |
20120264284 | MANUFACTURING METHOD FOR METAL GATE STRUCTURE - A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds. | 10-18-2012 |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 10-25-2012 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 12-06-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20120329285 | GATE DIELECTRIC LAYER FORMING METHOD - A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas. | 12-27-2012 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 01-10-2013 |
20130049141 | METAL GATE STRUCTURE AND FABRICATION METHOD THEREOF - A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer. | 02-28-2013 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 03-21-2013 |
20130078818 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure. | 03-28-2013 |
20130093064 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. | 04-18-2013 |
20130203230 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer. | 08-08-2013 |
20150069534 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. | 03-12-2015 |
20150214060 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer. | 07-30-2015 |
Patent application number | Description | Published |
20150067446 | DECODING METHOD, MEMORY STORAGE DEVICE AND REWRITABLE NON-VOLATILE MEMORY MODULE - A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased. | 03-05-2015 |
20150095741 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved. | 04-02-2015 |
20150186212 | DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased. | 07-02-2015 |