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Shang-Chih
Shang-Chih Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080258227 | STRAINED SPACER DESIGN FOR PROTECTING HIGH-K GATE DIELECTRIC - A semiconductor device pair is provided. The semiconductor device pair comprises a semiconductor substrate comprising a first gate structure with a first type polarity and a second gate structure with a second type polarity, the first and the second gate structures comprise a high-K gate dielectric. A plurality of oxygen-free offset spacer portions are adjacent either side of the respective first and second gate structures, each comprising a stressed dielectric layer, to induce a desired strain on a respective channel region while sealing respective high-K gate dielectric sidewall portions, wherein the oxygen-free offset spacer portions adjacent either side of the first gate structure and the oxygen-free offset spacer portions adjacent either side of the second gate structure are formed with different shapes. | 10-23-2008 |
Shang-Chih Chen, Jiadong Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 04-09-2009 |
| 20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 04-05-2012 |
Shang-Chih Hsieh, Yangmei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20130042158 | SCAN FLIP-FLOP CIRCUIT HAVING FAST SETUP TIME - A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode. | 02-14-2013 |
Shang-Chih Hsieh, Kaohsiung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090158104 | METHOD AND APPARATUS FOR MEMORY AC TIMING MEASUREMENT - A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured. | 06-18-2009 |
| 20090251872 | POWER SUPPLY ARCHITECTURE FOR STRUCTURAL ASIC - A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor. | 10-08-2009 |
Shang-Chih Hsieh, Taoyuan TW
| Patent application number | Description | Published |
|---|---|---|
| 20100019774 | ISOLATION CELL WITH TEST MODE - An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode. | 01-28-2010 |
Shang-Chih Lin, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120165878 | Bone Plate Structure - The present invention discloses an approximately Ļ-shaped improved bone plate structure, fixed on a bone of an animal for maintaining the relative positions of different portions of the bone. One of the other features of the present invention is that bone plate structure comprises at least one contouring portion for allowing the surgeons to intra-operatively adjusting the shape in accordance with the shape of the bone. Furthermore, the present invention may fit the bone with multi-axis, decreasing stress concentration, preventing the opening portion from being unsuitably covered and preventing the wound deformation from being pressed. | 06-28-2012 |
Shang-Chih Lin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20120303069 | RING AND BONE FIXATION SYSTEM - The present invention discloses a ring, embedded in a bone plate for fixing the relative position of a bone screw and the bone plate. The ring has a sidewall and the sidewall has a plurality of gaps. The ring further comprises a lower holding portion and an upper holding portion, the lower holding portion and the upper holding portion are utilized to hold the ring on one of the surface of the bone plate and the corresponding surface thereof respectively. The present invention is capable of fixing the screw to the through hole of the bone plate in various directions or angles so as to prevent the bone screw from passing through the joint, the smashed area or the area of severe osteoporosis thereof. Furthermore, the present invention is easy to operate, capable of avoiding damage and decreasing the trouble for the operator thereof. | 11-29-2012 |
Shang-Chih Lin, Hukou Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20090155681 | Structure of a battery set - The present invention provides a structure of a battery set including a battery body and a holder. The battery body has a circuit board disposed on a side of the battery body. The circuit board has a plurality of conductive pads. The holder with āUā shaped profile is provided on the side of the battery body with the circuit board and keeps a vacancy against the battery body. The filling body is formed in the vacancy between the battery body and the holder to envelop the circuit board and secure the connection of the holder and the battery body. | 06-18-2009 |