Patent application number | Description | Published |
20090001614 | SEMICONDUCTOR DEVICE WITH A BUFFER REGION WITH TIGHTLY-PACKED FILLER PARTICLES - An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent. | 01-01-2009 |
20140070397 | HIGH POWER SEMICONDUCTOR PACKAGE SUBSYSTEMS - A method and apparatus for incorporation of high power device dies into smaller system packages by embedding metal “coins” having high thermal conductivity into package substrates, or printed circuit boards, and coupling the power device dies onto the metal coins is provided. In one embodiment, the power device die can be attached to an already embedded metal coin in the package substrate or PCB. The power device die can be directly coupled to the embedded metal coin or the power device die can be attached to a metallic interposer which is then bonded to the embedded metal coin. In another embodiment, the die can be attached to the metal coin and then the PCB or package substrate can be assembled to incorporate the copper coin. Active dies are coupled to each other either through wire bonds or other passive components, or using a built-up interconnect. | 03-13-2014 |
20150055310 | SOLDER WETTABLE FLANGES AND DEVICES AND SYSTEMS INCORPORATING SOLDER WETTABLE FLANGES - An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems. | 02-26-2015 |
20150235933 | SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE PACKAGES, AND PACKAGING TECHNIQUES FOR IMPEDANCE MATCHING AND/OR LOW FREQUENCY TERMINATIONS - A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias. | 08-20-2015 |
Patent application number | Description | Published |
20110237211 | Reconfigurable Diversity Receiver - A method may include reconfigurably enabling one of a first downconverter and a second converter and disabling the other the second downconverter, wherein the first downconverter and the second downconverter are integral to a receiver unit of as wireless communications terminal. The method may also include frequency downconverting received wireless communication signals by the enabled downconverter. The method may also include processing the downconverted wireless communication signals by a primary path if the first downconverter is enabled, and processing the downconverted wireless communication signals by a diversity path if the second downconverter is enabled. | 09-29-2011 |
20120252393 | Technique to Generate Divide by Two and 25% Duty Cycle - A frequency divider with a twenty-five percent duty cycle is disclosed. A frequency divider may include an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase, a plurality of latches, and a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles. | 10-04-2012 |
20120252396 | Linearization Technique for Mixer - A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time. | 10-04-2012 |
Patent application number | Description | Published |
20090144528 | METHOD FOR RUNNING NATIVE CODE ACROSS SINGLE OR MULTI-CORE HYBRID PROCESSOR ACHITECTURE - Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task. | 06-04-2009 |
20100333075 | EXECUTING PLATFORM-INDEPENDENT CODE ON MULTI-CORE HETEROGENEOUS PROCESSORS - A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit. | 12-30-2010 |
20120296939 | PRESERVING EVENT DATA FOR LAZILY-LOADED MACRO COMPONENTS IN A PUBLISH/SUBSCRIBE SYSTEM - A method, system and computer program product for preserving event data for lazily-loaded macro components. Upon detecting an event published by a publisher, the logical channel of the detected event is identified. If one of the macro components to be lazily-loaded is a primary receiver for that logical channel (determined by performing a table-lookup of a data structure containing a listing of macro components and their associated logical channels for which they are to be the primary receivers), then the indication of the logical channel of the detected event along with the data of the published event are stored as a key/value pair in a data structure. Upon the macro component to be lazily-loaded having been loaded, the data of the published event associated with the logical channel for which the loaded macro component is a primary receiver is retrieved and transmitted to that logical channel. | 11-22-2012 |
20120297399 | AUTOMATICALLY UPDATING THE DISPLAY STATE OF THE USER INTERFACE OF A CLIENT DEVICE IN A PUBLISH/SUBSCRIBE SYSTEM - A method, system and computer program product for updating the display state of the user interface of a subscriber client. A macro component definition file is inspected to obtain the listing of events associated with each macro component listed in the macro component definition file. An event callback function is created for each macro component listed in the macro component definition file, where the callback function will update the displayed user interface of the subscriber client to be the display state of the macro component when one its associated events is published by the publisher. Upon detecting a published event, the event callback function associated with the published event is executed thereby automatically updating the display state of the user interface of the subscriber client to be the display state of the macro component associated with the published event. | 11-22-2012 |
20130247046 | PROCESSING CODE UNITS ON MULTI-CORE HETEROGENEOUS PROCESSORS - A virtual machine can be extended to be aware of secondary cores and specific capabilities of the secondary cores. If a unit of platform-independent code (e.g., a function, a method, a package, a library, etc.) is more suitable to be run on a secondary core, the primary core can package the unit of platform-independent code (“code unit”) and associated data according to the ISA of the secondary core. The primary core can then offload the code unit to an interpreter associated with the secondary core to execute the code unit. | 09-19-2013 |